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作 者:陈延博 杨兵[1] 康玄武 郑英奎[2] 张静[1] 吴昊[2] 刘新宇[2] Chen Yanbo;Yang Bing;Kang Xuanwu;Zheng Yingkui;Zhang Jing;Wu Hao;Liu Xinyu(College of Information,North China University of Technology,Beijing 100144,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)
机构地区:[1]北方工业大学信息学院,北京100144 [2]中国科学院微电子研究所,北京100029
出 处:《半导体技术》2022年第3期179-183,共5页Semiconductor Technology
基 金:国家自然科学基金资助项目(61804172,61874002);广东省重点领域研发计划资助项目(2019B010128001)。
摘 要:在Si基GaN上制备了与CMOS工艺兼容的高性能准垂直结构肖特基势垒二极管(SBD)。探索了在GaN体材料上基于Ti/Al/Ti/TiN结构的无金欧姆接触工艺,在650℃的N_(2)氛围退火60 s实现了较好的欧姆接触性能。通过采用电感耦合等离子体(ICP)干法刻蚀工艺,实现了低损伤的侧壁。同时采用TiN作为肖特基金属,实现了较低的开启电压。器件制备完成后对其进行分析表征。测试和分析结果表明,制备的无金工艺的准垂直GaN SBD实现了0.5 V的低开启电压,0.37 mΩ·cm^(2)的比导通电阻,理想因子为1.06,势垒高度为0.81 eV。器件的击穿电压为256 V,巴利加优值(BFOM)达到了177 MW/cm^(2)。研究表明,采用无金工艺制备GaN SBD具有技术上的可行性,该技术有望降低GaN SBD的制造成本。A high-performance quasi-vertical structure Schottky barrier diode(SBD) compatible with CMOS process was fabricated on Si-based GaN.The Au-free ohmic contact process based on Ti/Al/Ti/TiN structure on GaN bulk materials was explored,and a good ohmic contact performance was achieved by annealing at 650 ℃ in N_(2) atmosphere for 60 s.By adopting an inductively coupled plasma(ICP) dry etching process,low-damage sidewalls were realized.At the same time,TiN was used as Schottky metal to achieve a lower turn-on voltage.The device was analyzed and characterized after being prepared.The test and analysis results show that the prepared quasi-vertical GaN SBD with Au-free process achieves a low turn-on voltage of 0.5 V,a specific on-resistance of 0.37 mΩ·cm^(2),an ideality factor of 1.06 and a barrier height of 0.81 eV.The breakdown voltage of the device is 256 V,and the Baliga’s figure of merit(BFOM) reaches 177 MW/cm^(2).The study shows that it is technically feasible to fabricate GaN SBDs using the Au-free process,and the technology is expected to reduce the manufacturing cost of GaN SBDs.
关 键 词:Si基GaN 肖特基势垒二极管(SBD) 准垂直结构 无金工艺 电感耦合等离子体(ICP)刻蚀 TIN CMOS兼容工艺
分 类 号:TN311.7[电子电信—物理电子学]
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