LDPC编码的硬件实现及IC研究  

Hardware Implementation and IC Research of LDPC Encoding

作　　者：李锦明 贾博雄 Li Jinming;Jia Boxiong(School of Instrument and Electronics,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学仪器与电子学院,太原030051

出　　处：《单片机与嵌入式系统应用》2022年第4期65-69,共5页Microcontrollers & Embedded Systems

摘　　要：本文研究了一种用于近地空间通信的(8176,7154)低密度奇偶校验码。利用Vivado工具完成RTL级代码编写,并在完成FPGA硬件实现的基础上,通过Design Complier工具完成对编码RTL级代码的综合,并通过IC Complier工具完成对LDPC编码的后端IC设计流程,为芯片化进程提供了新的研究方向。A low-density parity-check code for near-earth space communication is studied in this paper.The RTL level code is written by using Vivado tool,and on the basis of completing the hardware implementation of FPGA,the coding RTL level code is synthesized by Design Complier tool,and the back-end IC design flow of LDPC coding is completed by IC Complier tool,which provides a new research direction for the chip process.

关 键 词：LDPC码 DC综合 IC设计 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]