81dBFS信噪比的低功耗四通道16位125Msps流水线型模数转换器设计  

Design of a Quad Low Power 16bit 125Msps Pipelined ADC with 81dB SNR

作　　者：张辉 李丹 王海军 高远 富浩宇 李婧 张煜彬 王紫琪 ZHANG Hui;LI Dan;WANG Haijun;GAO Yuan;FU Haoyu;LI Jing;ZHANG Yubin;WANG Ziqi(Shanghai Beiling Co.,Ltd.,Shanghai 200233,China.)

机构地区：[1]上海贝岭股份有限公司,上海200233

出　　处：《集成电路应用》2022年第3期16-17,共2页Application of IC

基　　金：工信部2019年869专项。

摘　　要：阐述一款4通道16位125Msps流水线ADC芯片的设计和测试,使用无采样保持、多比特的流水线ADC结构,并且辅以数字校准技术和P/N互补输入的运放结构,大大降低了芯片的功耗和噪声。This paper describes the design and test of a quad 16 bit 125 msps pipelined ADC chip. The pipelined ADC structure without sample and hold and multi bits is used, supplemented by digital calibration technology and P/N complementary input operational amplifier structure, which greatly reduces the power consumption and noise of the chip.

关 键 词：集成电路设计 ADC结构 数字校准 

分 类 号：TN792[电子电信—电路与系统] TN402