高速电流舵数模转换器减小时序失配的方法  

Methods for reducing the timing mismatch of high-speed currentsteering digital-to-analog converters

作　　者：付裕深 黄成宇 孙立猛 李学清[1,2] 杨华中 Yushen FU;Chengyu HUANG;Limeng SUN;Xueqing LI;Huazhong YANG(Department of Electronic Engineering,Tsinghua University,Beijing 100084,China;Beijing National Research Center for Information Science and Technology,Beijing 100084,China)

机构地区：[1]清华大学电子与工程系,北京100084 [2]北京信息科学与技术国家研究中心,北京100084

出　　处：《中国科学：信息科学》2022年第4期675-686,共12页Scientia Sinica(Informationis)

基　　金：国家自然科学基金(批准号:61934009)资助项目。

摘　　要：随着电流舵数模转换器(digital-to-analog converter,DAC)工作频率的提高,即使是数百飞秒的时序失配也会严重恶化高性能DAC的动态性能.在这一类DAC中,锁存驱动器模块直接控制电流源的开关切换,其时序直接影响电流舵DAC输出模拟信号的码间过渡动态特性.电流舵DAC锁存驱动器时序失配的主要来源,包括时钟网络延时失配、开关驱动晶体管的梯度失配和随机失配.一方面,在传统时钟网络中,不同位置节点间的失配是时钟网络延时失配的重要来源;另一方面,增加开关驱动晶体管尺寸可减少随机失配造成的延时偏差,但增加梯度失配造成的延时偏差.为了减小锁存驱动器时序失配提升DAC动态性能,本文提出了一种通过改变时钟网络连接方式减小时钟延时失配的方法,以及一种综合考虑梯度失配与随机失配的联合设计方法.为了验证所提方法的有效性,在65 nm工艺下设计了一个14b精度的DAC,流片测试结果表明在1 GS/s采样率、430 MHz信号带宽内,实测的无杂散动态范围(spurious-free dynamic range,SFDR)大于70 dB.与相同工艺下设计但并未采用本文所提出的时序优化方法的DAC测试结果对比表明,本文提出的时序优化方法以功耗从106 mW提升到160 mW为代价,将SFDR大于70 dB的信号带宽从210 MHz提升到430 MHz.As the operating frequency of the current-steering digital-to-analog converter(DAC)increases,a timing mismatch of hundreds of femtoseconds may significantly deteriorate the dynamic performance of the highperformance DAC.Herein,the latch module directly controls the switching of a group of current sources,and the timing synchronization directly affects the dynamic characteristics of the inter-symbol transition of the analog signal output by the current-steering DAC.Primary causes of the timing mismatch include the clock network delay mismatch,gradient mismatch of switch drive transistors,and random mismatch of switch drive transistors.The mismatch between the nodes at different locations in the traditional clock network is an important source of delay mismatch in the clock network.Notably,increasing the size of switch drive transistors can reduce the delay deviation caused by random mismatch but increase that by gradient mismatch.To reduce the latch timing mismatch and improve the dynamic performance of the DAC,this paper proposes a method to reduce the delay mismatch by changing the connection mode of the clock network and a joint design method considering both gradient and random mismatch.To verify the effectiveness of the proposed method,a 14-bit experimental DAC is fabricated via a 65-nm CMOS process.The measured spurious-free dynamic range(SFDR)is higher than 70dB at a 1-GS/s sampling rate for 430-MHz signal bandwidth.Compared with the measured results of a prior DAC designed using the same process excluding the timing optimization method,this work increases the signal bandwidth of SFDR>70 d B from 210 to 430 MHz at the expense of increased power consumption from 106 to160 mW.

关 键 词：时序失配 数模转换器(DAC) 时钟网络 梯度失配 随机失配 无杂散动态范围(SFDR) 

分 类 号：TN792[电子电信—电路与系统]