基于RISC-V处理器的TileLink与AXI4总线桥设计与实现  

Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor

作　　者：洪广伟 崔超 虞致国[1,2] 顾晓峰 HONG Guangwei;CUI Chao;YU Zhiguo;GU Xiaofeng(Engineering Research Center of Internet of Things Technology Applications,Ministry of Education,Wuxi 214122,Jiangsu,China;Department of Electronic Engineering,Jiangnan University,Wuxi 214122,Jiangsu,China)

机构地区：[1]物联网技术应用教育部工程研究中心,江苏无锡2140122 [2]江南大学电子工程系,江苏无锡214122

出　　处：《微电子学与计算机》2022年第4期100-108,共9页Microelectronics & Computer

基　　金：江苏省重点研发计划资助项目(BE2019003-2);中央高校基本科研业务费专项资金项目(JUSRP51510);江苏省研究生科研创新计划项目(KYCX20_1936)。

摘　　要：RISC-V是近年提出的一种开源精简指令集架构,TileLink总线是专为RISC-V处理器设计的片上总线.为使RISC-V处理器灵活适配更多已有的AXI4 IP资源,提出一种高效率TileLink与AXI4总线桥设计方案,其中由一系列功能子模块匹配总线间数据传输方式的差异,以流水线传输形式实现数据跨协议的传输,增加总线桥的数据吞吐量.在实现总线桥不同通道间的转换时,采用不同的仲裁策略,在AXI4总线的响应转换过程中,采用固定优先级仲裁,优先转换数据响应,保证系统整体运行效率;在AXI4总线的写数据和读数据事务转换过程中,采用轮询仲裁,保证写数据和读数据的公平性,均衡分配目标通道带宽,提高总线带宽利用率和系统传输效率.从模块级用TileLink随机测试激励对总线桥进行仿真验证,并通过在RISC-V处理器上挂载AXI4接口PCI Express根复合体,从FPGA系统级进行验证,结果表明,设计的总线桥能够正确转换协议,并且能较大提高系统带宽利用率.总线桥在SMIC 55 nm CMOS工艺下进行了ASIC实现,工作频率达714 MHz,版图面积405×405μm^(2).RISC-V is an open reduced instruction set architecture in recent years,and TileLink is a chip-scale interconnect standard designed for RISC-V.In order to use the existing AXI4 IP(Intellectual Property) resources flexibly in RISC-V processors,an efficient bus bridge design scheme between TileLink and AXI4 is proposed.A series of sub-modules match the transaction differences between Tilelink and AXI4,and complete the data transmission across protocols in the form of pipeline transmission,increasing the data throughput of the bus bridge.Different arbitration strategies are used to realize the conversion between different channels of the bus bridge.In the process of AXI4 bus response conversion,fixed-priority arbitration is used to preferentially convert read response,which improves the operating efficiency of the system.In the process of AXI4 bus write and read transactions conversion,round-robin arbitration is used to ensure the fairness of write and read transactions,balance the target channel bandwidth,and improve bus bandwidth utilization and system transmission efficiency.The functions of bus bridge are verified at the module level,by using Tilelink random test vectors.And by mounting the PCI Express root complex of AXI4 interface,the function of bus bridge is verified at the FPGA system level.The results show that the bus bridge can converse protocol correctly and greatly improve the system bandwidth utilization.The bus bridge is implemented in a SMIC 55 nm CMOS process.The frequency is 714 MHz and the area is 405×405 μm^(2) after physical design.

关 键 词：RISC-V 总线桥 TileLink总线 AXI4总线 流水线传输 

分 类 号：TP402[自动化与计算机技术]