基于阵列处理器的最小均方误差检测算法并行设计与实现  

Parallel design and implementation of minimum mean square error detection algorithm based on array processor

作　　者：刘帅[1] 蒋林 李远成[2] 山蕊 朱育琳 王欣 LIU Shuai;JIANG Lin;LI Yuancheng;SHAN Rui;ZHU Yulin;WANG Xin(College of Communication and Information Engineering,Xi’an University of Science and Technology,Xi’an Shaanxi 710054 China;College of Computer Science and Technology,Xi’an University of Science and Technology,Xi’an Shaanxi 710054,China;School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an Shaanxi 710121,China;College of Electrical and Control Engineering,Xi’an University of Science and Technology,Xi’an Shaanxi 710054,China)

机构地区：[1]西安科技大学通信与信息工程学院,西安710054 [2]西安科技大学计算机科学与技术学院,西安710054 [3]西安邮电大学电子工程学院,西安710121 [4]西安科技大学电气与控制工程学院,西安710054

出　　处：《计算机应用》2022年第5期1524-1530,共7页journal of Computer Applications

基　　金：国家自然科学基金资助项目(61834005,61772417);陕西省自然科学基金资助项目(2020JM-525)。

摘　　要：针对大规模多输入多输出(MIMO)系统中,最小均方误差(MMSE)检测算法在可重构阵列结构上适应性差、计算复杂度高和运算效率低的问题,基于项目组开发的可重构阵列处理器,提出了一种基于MMSE算法的并行映射方法。首先,利用Gram矩阵计算时较为简单的数据依赖关系,设计时间上和空间上可以高度并行的流水线加速方案;其次,根据MMSE算法中Gram矩阵计算和匹配滤波计算模块相对独立的特点,设计模块化并行映射方案;最后,基于Xilinx Virtex-6开发板对映射方案进行实现并统计其性能。实验结果表明,该方法在MIMO规模为128×4、128×8和128×16的正交相移键控(QPSK)上行链路中,加速比分别2.80、4.04和5.57;在128×16的大规模MIMO系统中,可重构阵列处理器比专用硬件减少了42.6%的资源消耗。In massive Multiple-Input Multiple-Output(MIMO)systems,Minimum Mean Square Error(MMSE)detection algorithm has the problems of poor adaptability,high computational complexity and low efficiency on the reconfigurable array structure.Based on the reconfigurable array processor developed by the project team,a parallel mapping method based on MMSE algorithm was proposed.Firstly,a pipeline acceleration scheme which could be highly parallel in time and space was designed based on the relatively simple data dependency of Gram matrix calculation.Secondly,according to the relatively independent characteristic of Gram matrix calculation and matched filter calculation module in MMSE algorithm,a modular parallel mapping scheme was designed.Finally,the mapping scheme was implemented based on Xilinx Virtex-6 development board,and the statistics of its performance were performed.Experimental results show that,the proposed method achieves the acceleration ratio of 2.80,4.04 and 5.57 in Quadrature Phase Shift Keying(QPSK)uplink with the MIMO scale of 128×4,128×8 and 128×16,respectively,and the reconfigurable array processor reduces the resource consumption by 42.6%compared with the dedicated hardware in the128×16 massive MIMO system.

关 键 词：大规模多输入多输出 最小均方误差算法 并行映射 阵列处理器 可重构 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]