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作 者:蒋欣[1] 刘晓栋 张亦姝 韩强[1] JIANG Xin;LIU Xiaodong;ZHANG Yishu;HAN Qiang(AVIC Xi’an Aeronautics Computing Technique Research Institute,Xi’an 710016,China;The Sixth Military Representative Office of Air Force Equipment Department in Xi’an Region,Xi’an 710016,China)
机构地区:[1]中航工业西安航空计算技术研究所,陕西西安710016 [2]空装驻西安地区第六军事代表室,陕西西安710016
出 处:《现代电子技术》2022年第13期13-16,共4页Modern Electronics Technique
摘 要:传统处理器间实现同步通信通常采用FPGA和同步时钟两种方式,前者存在FPGA与处理器集成度不高的问题,导致硬件设计的复杂度加剧;后者同步时钟设计复杂,系统会产生很大的软件开销。针对上述处理期间同步通信产生的不利问题,利用PowerPC系列处理器P2010的两个独立控制的UART控制器实现系统间的互联通信,同时配合软件约定的数据帧定义、缓冲区控制和握手机制,完成了一个数据处理模块上两个P2010处理器间的同步通信机制,减少了数据处理模块硬件电路设计的复杂度,增加了处理器间协调工作的途径,加强了数据处理模块使用的灵活性。相较于传统的同步通信方法,在不增加硬件成本和软件时间开销的同时提高了处理器间传输的稳定性和可靠性。The traditional synchronous communication between processors is usually realized by FPGA and synchronous clock.The former has the problem of low integration level between FPGA and processor,which aggravates the complexity of hardware design.The latter is complex in design of the synchronization clock,so the system will produce a lot of software overhead.In view of the adverse factors caused by synchronous communication during the above processing,the two independently⁃controlled UART controllers of processor P2010 in PowerPC series are used to realize the interconnection communication between systems,and completes the synchronous communication between two P2010 processors on one data processing module in combination with the data frame definition,buffer control and mobile phone holding system arranged by the software,which can reduce the complexity of hardware circuit design of data processing module,increase the way of coordination between processors,and strengthen the flexibility of data processing module.In comparison with the traditional synchronous communication methods,it improves the stability and reliability of transmission between processors while not increasing hardware cost and software time overhead.
关 键 词:串口通信 同步时钟 UART控制器 同步控制 互联通信 同步通信 硬件配置
分 类 号:TN915.9-34[电子电信—通信与信息系统]
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