基于65nm工艺的E类功率放大器设计  

Design of Class-E Power Amplifier Based on 65 nm Process

作　　者：任建[1] 郭国发 张本全 郑艳娜 REN Jian;GUO Guofa;ZHANG Benquan;ZHENG Yanna(School of Information Science and Engineering,Shenyang University of Technology,Shenyang 110870,China)

机构地区：[1]沈阳工业大学信息科学与工程学院,沈阳110870

出　　处：《微处理机》2022年第3期1-3,共3页Microprocessors

基　　金：辽宁省教育厅2020科研资助基金项目(LQGD2020009)。

摘　　要：为进一步提高射频功率放大器的效率与增益性能,设计一种工作在5GHz频率上的E类功率放大器。设计采用三级级联的D类功率放大器作为驱动级放大器,并包含一个工作在E类状态的cascode结构功率放大器,对负载回路进行负载牵引匹配优化。通过理论分析,使用Cadence软件Spectre对设计结构展开仿真。仿真结果得到器件在5 GHz及1.6 GHz~5.5 GHz区间的增益数据,证实设计具有很好的平坦度,同时得到功率附加效率、饱和输出功率的数值,证明其具有较好的线性度。本设计在5G通信技术领域具有重要应用及研究价值。In order to further improve the efficiency and gain performance of RF power amplifier,a class-E power amplifier operating at 5 GHz frequency is designed.A three-stage cascaded class-D power amplifier is taken as the driver amplifier,and a cascode power amplifier working in class-E state is included to optimize the load traction matching of the load circuit.Through theoretical analysis,the designed structure is simulated by using the software Cadence Spectre.The gain data of the device in 5GHz and 1.6 GHz~5.5 GHz are obtained by simulation,which proves that the design has good flatness,and the values of power added efficiency and saturated output power are obtained,which proves that it has good linearity.The design takes on important application and research value in the field of 5G communication technology.

关 键 词：E类功率放大器 Cascode结构 驱动级放大器 功率附加效率 饱和输出功率 

分 类 号：TN402[电子电信—微电子学与固体电子学]