基于新型并行LMS算法的数字预失真器设计  

PA Digital Predistorter Based on Novel Parallel LMS Algorithm

作　　者：曾德军 ZENG Dejun(Southwest China Institute of Electronic Technology,Chengdu Sichuan 611731,China)

机构地区：[1]中国西南电子技术研究所,四川成都611731

出　　处：《通信技术》2022年第6期801-806,共6页Communications Technology

摘　　要：针对功放(Power Amplifier,PA)非线性失真问题,提出了一种运用于数字预失真器(Digital Predistorter,DPD)中的新型最小均方(Least Mean Square,LMS)自适应算法结构。该算法的主要特点是用3个独立并行实数滤波器支路结构实现一个复数滤波器。相比于传统LMS算法,这种结构能够极大地减小算法的实现复杂度,缩减现场可编程门阵列(Field Programmable Gate Array,FPGA)和数字信号处理器(Digital Signal Processor,DSP)的硬件实现资源。实验结果表明,使用这种算法结构的DPD能够显著地提高功放的线性度。Aiming at the nonlinear distortion problem of PA(Power Amplifier),this paper presents a novel LMS(Least Mean Square) adaptive algorithm structure used in DPD(Digital PreDistorter).The three-parallel real filter structure is employed to realize a complex filter by forming three separate data streams and three independent real filters.Compared with the traditional LMS algorithm,this structure can greatly reduce the complexity of the computation and it is more efficient to be implemented in FPGA(Field Programmable Gate Array) and DSP(Digital Signal Processor).Finally,the experiment results indicate that the DPD using this algorithm structure can significantly improve the linearity of the PA.

关 键 词：数字预失真器 功放 最小均方 并行滤波器 

分 类 号：TN722.75[电子电信—电路与系统]