基于密码芯片的DDR加速器的设计与实现  

Design and Implementation of DDR Accelerator Based on Cryptographic Chip

作　　者：姜冬梅 何欣霖 李军 JIANG Dongmei;HE Xinlin;LI Jun(Chengdu 30JAVEE Microelectronics Co.,Ltd.,Chengdu Sichuan 610041,China)

机构地区：[1]成都三零嘉微电子有限公司,四川成都610041

出　　处：《通信技术》2022年第6期807-812,共6页Communications Technology

摘　　要：在安全服务器应用领域,基于对称算法的密码芯片需要读写访问大量、离散的密钥和初始向量(Intial Vector,IV)数据。利用密钥和IV数据的时间局部性和空间局部性,提出了一种预读与高速缓冲存储器(cache)相结合的双倍速率同步动态随机存取存储(Double Data Rate Synchronous Dynamic Random Access Memory,DDR)加速器,来解决密钥和IV的存储容量和访问效率的问题,并采用Verilog硬件描述语言完成DDR加速器的实现。最后基于芯动的DDR控制器和镁光的DDR3模型,进行有、无加速器的性能对比试验,试验表明DDR硬件加速器较大地提高了DDR对离散数据的访问性能,解决了密钥和IV存储中的容量和效率的问题。In the field of secure server applications,cryptographic chips based on symmetric algorithms need to access a lot of discontinuous keys and initial vectors.According to the temporal locality and spatial locality of the key and IV data,this paper proposes a DDR(Double Data Rate Synchronous Dynamic Random Access Memory) hardware accelerator combining pre-fetch and cache,which is used to solve the problems of storage capacity and access efficiency of keys and IVs,and uses the Verilog hardware description language to complete the implementation of the DDR accelerator.Finally,based on INNOR DDR controller and Micron’s DDR3 model,a performance comparison test with and without an accelerator is conducted.Experiments indicate that the DDR hardware accelerator greatly improves the access performance of discontinuous data,and solves the problems of storage capacity and access efficiency of keys and IVs.

关 键 词：DDR加速器 高速缓冲存储器 预读 流水线 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]