SiC MOSFET功率模块的并联均流研究  

Research on Parallel Current Sharing of SiC MOSFET Power Modules

作　　者：黄轶愚 谭会生[1,2] 吴义伯 戴小平 Huang Yiyu;Tan Huisheng;Wu Yibo;Dai Xiaoping(College of Railway Transportation,Hunan University of Technology,Zhuzhou 412007,China;Hunan Province Higher Education Key Laboratory of Modeling and Monitoring on the Near-Earth of Electromagnetic Environments,Changsha University of Science and Technology,Changsha 410015,China;School of Microelectronics,Wuhan University,Wuhan 430012,China;Coresing Semiconductor Technology Co.,Ltd.,Zhuzhou 412001,China)

机构地区：[1]湖南工业大学轨道交通学院,湖南株洲412007 [2]长沙理工大学近地空间电磁环境监测与建模湖南省普通高校重点实验室,长沙410015 [3]武汉大学微电子学院,武汉430072 [4]湖南国芯半导体科技有限公司,湖南株洲412001

出　　处：《半导体技术》2022年第6期481-487,共7页Semiconductor Technology

基　　金：湖南省教育厅科学研究重点资助项目(20A163);长沙理工大学近地空间电磁环境监测与建模湖南省普通高校重点实验室开放基金资助项目(N201903)。

摘　　要：采用多芯片并联的方法可提高SiC MOSFET功率模块的应用电流等级,但由于并联支路的杂散参数差异导致流过各并联芯片的电流不一致,这将影响功率模块的可靠性。建立了典型的三芯片并联半桥模块电路模型,分别改变功率回路和驱动回路的杂散参数并计算其不均衡度,使用双脉冲测试方法测试相应的开、关电流,计算其电流不均衡度。研究了模块内部各杂散参数对多芯片并联均流能力的影响,结果表明,功率模块的瞬态均流能力受源极电感影响较大,稳态均流能力受杂散电阻影响较大。提出了一种基于芯片源极互连降低并联均流不均衡度的方法,仿真结果表明该方法可有效降低源极参数对多芯片并联均流能力的影响。The method of multi-chip parallel can be used to improve the application current level of the SiC MOSFET power module.However,the current flowing through each parallel chip is inconsistent due to the difference of stray parameters of parallel branches,which will affect the reliability of the power module.The circuit model of typical 3-chip parallel half-bridge module was established.The stray parameters of the power loop and the drive loop were changed respectively,and the imbalance degrees were calculated.The corresponding on-off currents were tested by the double pulse test method,and the imbalance degree of current was calculated.The influences of various stray parameters in the module on the current sharing capacity of the multi-chip parallel were studied.The results show that the transient current sharing capability of the power module is greatly affected by the source inductance,and the static current sharing capability is significantly affected by the stray resistance.A method to reduce the imbalance of parallel current sharing based on chip source interconnection was proposed.The simulation results show that this method can effectively reduce the effect of source parameters on the current sharing capacity of the multi-chip parallel.

关 键 词：功率模块 封装技术 杂散电感 并联均流 源极互连 

分 类 号：TN45[电子电信—微电子学与固体电子学] TN386.1