加扰技术对模数转换器性能的影响  

Effect of Injecting Dither on A/D Converter Performance

作　　者：朱蓓丽 岂飞涛 张琳 刘涛[1,2] 刘海南[1,2] 滕瑞[1,2] 李博[1,2] 赵发展 罗家俊[1,2] 韩郑生[1,2,3] ZHU Beili;QI Feitao;ZHANG Lin;LIU Tao;LIU Hainan;TENG Rui;LI Bo;ZHAO Fazhan;LUO Jiajun;HAN Zhengsheng(Institute of Microelec.,Chinese Academy of Sci.,Beijing 100029,P.R.China;Key Lab.of Sci.and Technol.on Silicon Dev.,Chinese Academy of Sci.,Beijing 100029,P.R.China;Univ.of Chinese Academy of Sci.,Beijing 100049,P.R.China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院硅器件技术重点实验室,北京100029 [3]中国科学院大学,北京100049

出　　处：《微电子学》2022年第2期323-328,共6页Microelectronics

摘　　要：分析了加扰技术改善ADC性能的基本原理,通过选择合适的扰动信号注入到理想量化器模型中进行仿真,验证了加扰技术能够随机化量化误差的周期性三角形分布。在加扰技术的实际应用中,首先基于10 bit 25 MS/s Pipelined ADC模型完成加扰仿真,仿真得到ADC的SFDR由74.69 dB提高到了85 dB。然后对两种ADC芯片进行加扰实验,该加扰技术使两种ADC芯片的SFDR分别提高了8.29 dB和5.97 dB。理论仿真和实验验证了加扰技术可以明显提高ADC的SFDR,为后期ADC内部集成加扰电路模块做好了准备工作。The theory of injecting dither signal was analyzed to improve the performance of ADC. An appropriate dither signal was selected to inject into the ideal quantized model. The simulation demonstrated that the dither injecting technique could randomize the periodic triangular distribution of quantization error. In the practical application of the dither injecting technique, firstly, the dither injecting simulation was completed based on 10 bit 25 MS/s pipelined ADC model, and the SFDR of ADC was improved from 74.69 dB to 85 dB. Then, the dither injecting test was carried out for two kinds of ADC chips. The SFDR of ADC chips were increased by 8.29 dB and 5.97 dB respectively depending on dither injecting technique. The experiment gave a conclusion that the dither injection technique could significantly improve SFDR of ADC, made a full preparation for the integration of noise circuit module into ADC.

关 键 词：加扰 ADC 量化误差 SFDR 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792