基于MIPS32指令集对斐波那契数列的设计与实现  

Design and Implementation of Fibonacci Sequence Based on MIPS32 Instruction Set

作　　者：吴亚文 韩跃平[1] 唐道光 Wu Yawen;Han Yueping;Tang Daoguang(College of Information and Communication Engineering,North University of China,Taiyuan 030051,China;Shanxi 100 Trust Information Technology Co.,Ltd.)

机构地区：[1]中北大学信息与通信工程学院,太原030051 [2]山西百信信息技术有限公司

出　　处：《单片机与嵌入式系统应用》2022年第8期70-74,共5页Microcontrollers & Embedded Systems

摘　　要：基于MIPS32指令集架构设计了一款可以实现斐波那契数列的处理器。处理器设计没有运用经典五级流水线技术,而是设计了六级流水线,并且采用数据定向前推的方法解决数据相关问题以及延迟转移,采用分支延迟槽的方法解决控制相关问题。设计完成后,使用Modelsim仿真软件对处理器进行指令集及功能仿真,仿真结果表明,在50 MHz时钟频率下处理器指令集及功能正常运行。最后,在FPGA开发板上进行验证,实现了软件与硬件交互,验证结果表明,该设计可以正确实现斐波那契数列,满足预期设计要求。Based on MIPS32 instruction set architecture,a processor which can realize Fibonacci sequence is designed.The processor design does not use the classical five stage pipeline technology,but designs a six stage pipeline,and uses the data oriented push forward method to solve the data related problems,as well as the methods of delay transfer and branch delay slot to solve the control related problems.After the design is completed,the instruction set and function of the processor are simulated by Modelsim simulation software.The simulation results show that the instruction set and function of the processor operate normally at the clock frequency of 50 MHz.Finally,it is verified on the FPGA development board to realize the interaction between software and hardware.The verification results show that the Fibonacci sequence can be realized correctly and meet the expected design requirements.

关 键 词：MIPS32 处理器 斐波那契数列 FPGA 

分 类 号：TN402[电子电信—微电子学与固体电子学]