应用QFN封装的CMOS运算放大器芯片设计  

Design of CMOS Operational Amplifier Chip by Using QFN Package

作　　者：陈宏[1] 杨树 郭清[1] 刘立[1] CHEN Hong;YANG Shu;GUO Qing;LIU Li(College of Electrical Engineering,Zhejiang University,Hangzhou 310027,China)

机构地区：[1]浙江大学电气工程学院,杭州310027

出　　处：《实验室研究与探索》2022年第4期103-106,共4页Research and Exploration In Laboratory

摘　　要：设计了一种提高晶圆利用率和产出的小尺寸CMOS运算放大器贴片封装工艺。采用两级放大电路实现大功率输出,按照CMOS制造工艺要求,在16μm×16μm设计折叠型7层版图的集成电路,按照QFN封装的特点增加散热能力。测试结果证明,该设计电性能好,达到CMOS制造工艺的技术要求。这种创新设计的版图面积和芯片体积小、质量轻、集成度高,可降低芯片的工业制造成本,对解决晶圆利用率低和产出低的问题具有实践价值。In order to improve the utilization rate of wafer and output,a new design for the operational amplifier with patch packaging is presented in this paper.The two-level circuits are designed to improve the output power.The folded type MOS chips and 7 layers are designed according to the CMOS manufacturing process.The feature of Quad Flat No-leads Package is utilized to dissipate heat for the operational amplifier effectively.The design is checked and shows good electrical quality to satisfy the technical requirements of CMOS manufacturing process.The innovative design has the reduced occupying area,the volume,and the weight with high integration to eliminate the cost of IC industrial production,improves the productivity,and solves the issues of the low utilization rate of wafer and low output,which demonstrates the important practice value.

关 键 词：芯片设计 集成电路 CMOS工艺 封装 运算放大器 

分 类 号：TN402[电子电信—微电子学与固体电子学]