基于STT-MRAM的高可靠性、多位并行读出存内计算方案  

A high reliability,multi-bit parallel readout in-memory computing scheme based on STT-MRAM

作　　者：袁磊 陈俊杰[1] 卓鹏福 王少昊 YUAN Lei;CHEN Junjie;ZHUO Pengfu;WANG Shaohao(Jinjiang Joint Institute of Microelectronics,Jinjiang Science and Education Park,Fuzhou University,Jinjiang 362200,Fujian,China)

机构地区：[1]福州大学晋江微电子研究院,福建晋江362200

出　　处：《微电子学与计算机》2022年第8期119-126,共8页Microelectronics & Computer

基　　金：国家重点研发计划(2018YFB0407603)。

摘　　要：存内计算技术是解决传统冯·诺伊曼计算架构面临瓶颈的最有效的技术路径之一.基于自旋转移矩-磁随机存储器(STT-MRAM)的存内计算方案尽管具有非易失性、低功耗、高耐久性等优势,但却因其较小的感测裕度对灵敏放大器(SA)设计的读可靠性提出了挑战.尽管基于两个晶体管和两个磁隧道结(2T2MTJ)单元的存内计算方案能有效提升读感测裕度与位运算正确率,存储阵列的面积却成倍增加.本文针对1T1MTJ单元,提出一种高可靠性、多位并行读出存内计算方案,采用了三组参考单元支路结构,结合改进型多位电流型灵敏放大器(MBCSA)进行支路电流运算.结合MTJ紧凑模型与SMIC 40nm工艺的仿真结果表明,在典型条件下,该方案的读操作正确率比采用预充电电流型灵敏放大器(PCSA)的1T1MTJ方案和2T2MTJ方案分别提升了4.07%和1.65%;在小磁阻比、低电源电压条件下也展现了更高的读操作正确率与良好的鲁棒性.此外,该方案可在6 ns周期内同时对两组存储单元进行“AND”、“OR”逻辑运算,实现了四种位逻辑运算结果的多位并行读出.In-memory computing technology is one of the most effective ways to solve the bottleneck of traditional von Neumann computing architecture.Although STT-MRAM has the advantages of non-volatile,low power consumption and high durability,its small sensing margin poses a challenge to the read reliability of sensitive amplifier(SA)design.Although the in-memory computing scheme based on two transistors and two magnetic tunnel junction(2T2MTJ)cells can effectively improve the read sensing margin and bit operation accuracy,the area of the memory array increases exponentially.For 1T1MTJ unit,we proposed a high reliability,multi-bit parallel readout in-memory computing scheme using an enhanced multi-bit current-sensitive amplifier(MBCSA)for branch current calculation and three independent reference units.The simulation results indicates that,when compared with the 1T1MTJ and 2T2MTJ schemes with precharge current-sensitive amplifier,the proposed scheme can improve the accuracy rates of the bitwise in-memory computing by 4.07%and 1.65%,respectively,in the typical case,and further enhance the read accuracy and robustness when with a small TMR and a low V _(DD).Moreover,the proposed scheme can simultaneously perform“AND”and“OR”bitwise logical operations for two pairs of data units in a 6 ns read cycle as well as the results of“NAND”and“NOR”and output four kinds of bit logic operation results.

关 键 词：磁随机存储器 存内计算 高可靠性 多位并行读出 

分 类 号：TN432[电子电信—微电子学与固体电子学]