A modeling method of algorithm-hardware based on SysML  

作　　者：Liu Yue Zhao Chun Zhang Lin 

机构地区：[1]Computer School,Beijing Information Science and Technology University,Beijing 100101,P.R.China [2]School of Automation Science and Electrical Engineering Beihang University,Beijing 100191,P.R.China

出　　处：《International Journal of Modeling, Simulation, and Scientific Computing》2022年第3期74-97,共24页建模、仿真和科学计算国际期刊（英文）

基　　金：This work is supported by the National Key R&D Program of China(Grant No.2018YFB1701602).

摘　　要：In the process of complex product design,modeling in different fields and different disciplines is often involved.Designers often face many different development kits,platforms,and theories,among which significant differences exist.Especially in the process of algorithm-hardware implementation,it is necessary to have mastery of the knowledge including algorithm,hardware,circuit,and system engineering.In this paper,a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling.By using the method,the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model.In this method,a method of graphical system modeling based on SysML is used,where the elements of the algorithm-hardware model are described by SysML graphical models.Then,the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language.At last,a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

关 键 词：SYSML VHDL FPGA MDA 

分 类 号：TN9[电子电信—信息与通信工程]