基于FPGA的雷达A式显示电路设计  

Design of radar A-display circuit based on FPGA

作　　者：阮成肖 Ruan Chengxiao(Jiangsu Automation Research Institute,Lianyungang 222061,China)

机构地区：[1]江苏自动化研究所,江苏连云港222061

出　　处：《电子技术应用》2022年第8期24-28,共5页Application of Electronic Technique

摘　　要：为了实现对雷达显示技术的优化与升级,设计实现了一种基于FPGA的雷达A式显示电路,采用FPGA集成雷达显示IP核实现雷达前端信号的采样、处理及显示。该设计利用FPGA芯片庞大的可编程逻辑单元以及丰富的成熟IP核的优势,实现了单片逻辑芯片实现雷达输入信号的接收、采样、变换以及显示的功能,简化了以往雷达显示电路的硬件结构,降低了信号的显示延迟,整体提升雷达显示性能。同时该设计可以通过进一步修改内部IP核实现其他雷达显示方式,使其具备硬件设备的通用性和可扩展性。In order to optimize and upgrade radar display technology,a radar A-display circuit based on FPGA is designed and implemented in this paper.The FPGA integrated radar display IP core is used to realize the sampling,processing and displaying of radar front-end signals.The design takes advantage of the huge programmable logic unit of the FPGA chip.The rich mature IP cores realize the functions of receiving,sampling,transforming and displaying the radar input signal of the single-chip logic chip.It simplified the hardware structure of the previous radar display system,reduced the display delay of the signal,and improved the radar display performance.At the same time,the design can realize other radar display methods by further modifying the internal IP core,so that it has the versatility and scalability of hardware devices.

关 键 词：现场 可编程逻辑芯片 IP核 雷达视频 显示技术 

分 类 号：TN952[电子电信—信号与信息处理]