基于分解的多路选择器工艺映射方法设计  

Design of Technology Mapping Method Based on Decomposition for Multiplexers

作　　者：谢尚銮 惠锋 刘佩 王晨阳 张立 XIE Shangluan;HUI Feng;LIU Pei;WANG Chenyang;ZHANG Li(East Technology,Inc.,Wuxi 214072,China)

机构地区：[1]无锡中微亿芯有限公司,江苏无锡214072

出　　处：《电子与封装》2022年第8期48-53,共6页Electronics & Packaging

摘　　要：针对Virtex-7系列FPGA架构,提出了一种基于分解的多路选择器工艺映射方法。选取多个细粒度规则多路选择器作为基准单元,将对应的优质工艺网表保存为模板,将N选1多路选择器递归分解为若干层紧密连接的基准单元并基于模板实现其优化映射。对比所提方法与综合工具Vivado及ABC的多路选择器工艺映射效果,实验数据表明该方法与Vivado相比可平均减少1.01%的查找表(LUT)开销与5.61%的时延,与ABC相比可平均减少20.82%的LUT开销与29.51%的时延,而且该方法时间复杂度低,平均运行速度比ABC快4.28倍。Targeting at the hardware structure of Virtex-7 series FPGA,a decomposition-based technology mapping method for multiplexers is proposed.Specified fine-grained full-multiplexers are chosen as reference cells,and their high-quality technology netlists are saved as templates.N-to-1 multiplexers are recursively decomposed into several levels of cohesive reference cells.The templates are employed to accomplish the technology mapping of N-to-1 multiplexers.Multiplexers mapping results of the proposed method and synthesis tools of Vivado and ABC are compared,and experimental results show that the proposed method can reduce look-up table(LUT)utilization by 1.01%and decrease circuit delay by 5.61%on average compared with Vivado,and outperform ABC in the same comparison parameters by 20.82%and 29.51%respectively.Meanwhile,owing to the low time complexity of this method,its running speed is 4.28 times faster than ABC on average.

关 键 词：FPGA 多路选择器 工艺映射 分解 

分 类 号：TN402[电子电信—微电子学与固体电子学]