基于初始解优化的FPGA布线方法  

FPGA Routing Method Based on Initial Solution Optimization

作　　者：惠锋 谢尚銮 HUI Feng;XIE Shangluan(East Technology,Inc.,Wuxi 214072,China)

机构地区：[1]无锡中微亿芯有限公司,江苏无锡214072

出　　处：《电子与封装》2022年第8期59-63,共5页Electronics & Packaging

摘　　要：针对自主研发的现场可编程门阵列(FPGA)芯片,提出了一种基于初始解优化的FPGA布线方法。根据逻辑片布线结构,通过简单模式匹配对网表的逻辑单元引脚进行重构来生成低布线拥挤度的初始解,并在布线过程中按节点与漏端相结合的布线策略实现解的快速收敛。实验数据表明,所提方法在全局布线阶段可使拥塞数量下降16.6%,在详细布线阶段可使累计拥塞数量下降9.8%,而且运行时间缩短了7.8%,关键路径裕量提升了17.2%。The routing method based on initial solution optimization is proposed for self-design field programmable gate array(FPGA).According to the logic chip routing structure,the logic cell pins of the netlist are reconstructed by simple pattern matching to generate initial solutions with low routing congestion.The routing strategy combining the nodes and sinks is used in the routing progress to accelerate the convergence of the solution.Experimental results show that the proposed method reduces the number of congestion by 16.6%in the global routing stage,decreases the cumulative number of congestion by 9.8%in the detail routing stage,reduces the running time by 7.8%and improves the critical path margin by 17.2%.

关 键 词：现场可编程门阵列 布线 引脚重构 初始解 拥塞 

分 类 号：TN402[电子电信—微电子学与固体电子学]