基于FPGA的卷积神经网络加速优化方法  

FPGA-Based Accelerated Optimization Method of Convolutional Neural Network

作　　者：林朋雨 郭杰[1,2] LIN Peng-yu;GUO Jie(State Key Laboratory of Integrated Services Networks,Xidian University,Xi'an Shanxi 710071,China;School of Telecommunications Engineering,Xidian University,Xi'an Shanxi 710071,China)

机构地区：[1]西安电子科技大学综合业务网理论及关键技术国家重点实验室,陕西西安710071 [2]西安电子科技大学通信工程学院,陕西西安710071

出　　处：《计算机仿真》2022年第7期371-374,450,共5页Computer Simulation

基　　金：国家自然科学基金青年基金项目(61501346)。

摘　　要：利用当前方法对卷积神经网络进行加速优化处理时,没有分析卷积神经网络前向传播结构,导致卷积神经网络的资源浪费严重以及计算量过大,存在资源消耗率高和网络计算量大的问题,提出基于FPGA的卷积神经网络加速优化方法。构建卷积神经网络前向传播模型,分析了传播结构中卷积层、池化层、激活函数和填充的特点。根据分析结果利用FPGA构建加速器,通过卷积层并行加速可行性分析、基本模块设计、通道并行卷积层加速设计实现卷积神经网络的加速优化,利用流水线方法对卷积窗口进行操作,通过全并行乘法-加法树模块减少卷积神经网络的计算量。实验结果表明,所提方法的资源消耗率低、网络计算量小。In the process of accelerating the optimization of the convolutional neural network,the traditional method ignores the forward propagation structure of the convolutional neural network,resulting in the waste of convolutional neural network resources and a large amount of calculation.Therefore,this paper puts forward a convolutional neural network acceleration optimization method based on FPGA.The forward propagation model of the convolution neural network was constructed,and the characteristics of the convolution layer,pooling layer,activation function and filling were investigated in detail.FPGA was applied to build accelerators.The convolution neural network was optimized by the feasibility analysis of convolution layer parallel acceleration,basic module design and channel parallel convolution layer acceleration design.The pipeline method was utilized to operate the convolution window,and the full parallel multiplication and addition tree module were used to reduce the computation of the convolution neural network.The results show that the method has low resource consumption and a small amount of network computation.

关 键 词：卷积神经网络 前向传播模型 加速器 加速优化方法 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]