基于28nm数字芯片的分步式时钟树综合设计  

Clock tree syntehsis of step by step based on 28nm digital chip

作　　者：翟金标 李建成 ZHAI Jin-biao;LI Jian-cheng(Xiangtan University)

机构地区：[1]湘潭大学物理与光电工程学院 [2]湖南德雅华兴科技研究院

出　　处：《中国集成电路》2022年第8期40-44,共5页China lntegrated Circuit

摘　　要：针对常规时钟树综合得到的时钟偏移大[1]、使用的时钟树单元多、功耗大等对芯片整体设计产生的不利因素,提出了一种分步式时钟树综合方法,即时钟树综合分两步走,第一步主要完成公共路径的时钟树综合,将时钟源转移到芯片中心处,第二步在新的时钟源即芯片中心处向四周做时钟树,由于时钟源位于芯片中心位置,这有利于平衡时钟源到叶节点的延迟。对两种时钟树综合方法进行比较,实验结果表明:分步式时钟树综合的时钟偏移比Innovus工具推荐的时钟树综合少了77ps,时钟树上使用的单元数量少了4458个,并且功耗降低了10mw左右。In view of the disadvantages of the integrated chip design,such as large clock offset,many clock tree elements and high power consumption,which are obtained by the conventional clock tree synthesis.Put forward a step by step the clock tree synthesis method,the comprehensive two-step clock tree,the first step is mainly completed the clock tree synthesis of public path,moving clock source into the center of the chip,the second step to the new clock source-the center place again around the clock tree,because the clock source is located in the center of the chip,this will help balance the clock source to the delay of leaf nodes.Two methods of clock tree synthesis are compared.The experimental results show that the clock shift of the distributed clock tree synthesis is 77ps less than the clock tree synthesis recommended by Innovus tool,the number of cells used in the clock tree is 4458 less,and the power consumption is reduced by about 10mW.

关 键 词：时钟偏移 时钟树综合 低功耗 物理设计 

分 类 号：TN402[电子电信—微电子学与固体电子学]