深低温大功率电阻阵列封装结构研究  

Research on the package structure of deep low-temperature and high-power resistor array

作　　者：孙权 莫德锋[1,2] 刘大福[1,2] 龚海梅[1,2] Sun Quan;Mo Defeng;Liu Dafu;Gong Haimei(State Key Laboratories of Transducer Technology,Shanghai Institute of Technical Physics,Chinese Academy of Sciences,Shanghai 200083,China;Key Laboratory of Infrared Imaging Materials and Detectors,Shanghai Institute of Technical Physics,Chinese Academy of Sciences,Shanghai 200083,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院上海技术物理研究所传感技术联合国家重点实验室,上海200083 [2]中国科学院上海技术物理研究所红外成像材料与器件重点实验室,上海200083 [3]中国科学院大学,北京100049

出　　处：《红外与激光工程》2022年第8期422-430,共9页Infrared and Laser Engineering

基　　金：中国科学院重点部署项目(ZDRW-CN-2019-3);中国科学院青年创新促进会(2018274)。

摘　　要：电阻阵列的封装需求向着集成度高、大功率、深低温方向发展。为了满足130 K以下低温工作、稳态功率100 W以上的深低温应用需求,提出了一种利用液氮进行制冷的集成封装结构,并利用有限元仿真和实测验证相结合的方法验证了装置的制冷能力。结果表明,热沉钼与陶瓷电极板的厚度均为2 mm的情况下,加热功率在0.1~192.76 W区间内,有限元仿真得到的温度与实测温度最大误差小于7.67%,引起误差的主要原因是封装结构件的体热阻及界面热阻随温度发生变化而仿真时采用恒定热阻。结构能够在加热功率小于211.90 W的工况下正常工作。在设计的100 W稳定加热工况下,芯片衬底温度不高于101.9 K,热应力为5.66 MPa,满足设计要求。The packaging requirements of resistor arrays are high integration,high power,and deep low temperature.To make the resistor arrays work normally below 130 K when the heating power is over 100 W,an integrated package structure using liquid nitrogen for refrigeration is proposed.Finite element simulation and experimental verification are carried out.The results show that the overall error between the temperature distribution obtained by finite element simulation and the physical experiment is less than 7.67%when the thickness of the molybdenum heat sink and the ceramic electrode plate are both 2 mm and the heating power is in the range of 0.1-192.76 W.The error mainly comes from the body and interface thermal resistance of the package structure changing with temperature,while the constant thermal resistance is used in the simulation.The structure can work normally when the heating power is less than 211.90 W.Under the designed stable 100 W heating condition,the chip substrate temperature is not higher than 101.9 K,and the thermal stress is 5.66 MPa,which meets the design requirements.

关 键 词：有限元仿真 电阻阵列 封装结构 温度分布 

分 类 号：TN21[电子电信—物理电子学]