面向超高清微显示器的20Gbps低抖动CDR设计  

Design of a 20 Gbps Low Jitter Clock Data Recovery Circuit for Ultra HD Micro Display

作　　者：吴浩[1] 季渊[1,2] 郑志杰 穆廷洲 WU Hao;JI Yuan;ZHENG Zhijie;MU Tingzhou(Microelectronics Research and Development Center,Shanghai University,Shanghai,200072,CHN;School of Mechatronic Engineering and Automation,Shanghai University,Shanghai,200072,CHN)

机构地区：[1]上海大学微电子研究与开发中心,上海200072 [2]上海大学机电工程与自动化学院,上海200072

出　　处：《固体电子学研究与进展》2022年第4期323-328,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(61774101)。

摘　　要：针对超高清硅基微显示器对接口电路高信号带宽的要求,设计了一款20 Gbps的双环路低抖动时钟数据恢复电路。该电路工作在锁频环路时,锁定检测器控制电荷泵电流逐步减小,有效降低控制电压纹波,并采用LDO镜像结构抑制环形压控振荡器电源纹波及不同电源节点间的纹波串扰,减少环路噪声。测试结果表明,提出的微显示器架构和设计的CDR电路可实际应用于超高清硅基OLED微显示器,恢复出的20 Gbps数据峰峰值抖动为36.8 ps,捕获范围为17.4~21.7 GHz,功耗为43 mW。A 20 Gbps dual loop low jitter clock data recovery circuit was designed for the requirements of high-definition silicon-based micro display for high signal bandwidth of interface circuit.When the circuit worked in frequency locking loop,the lock detector controlled the charge pump current to decrease gradually and effectively lowered the control voltage ripple.The LDO mirror structure was used to suppress the power ripple of the ring oscillator and reduce the ripple crosstalk between different power nodes,thus reduced the loop noise.The test results show that the proposed micro display architecture and CDR circuit can be applied to ultra-high-definition silicon-based OLED micro display.The peak-to-peak jitter of recovered 20 Gbps data is 36.8 ps,the capture range is17.4-21.7 GHz,and the power consumption is 43 mW.

关 键 词：微显示器 时钟数据恢复电路 电源纹波 低抖动 

分 类 号：TN402[电子电信—微电子学与固体电子学]