一种环路带宽自适应调整的时钟数据恢复电路  

A Clock Data Recovery Circuit with Adaptive Loop Bandwidth Adjustment

作　　者：常承 韦保林[1] 韦雪明[1] 侯伶俐 徐卫林[1] CHANG Cheng;WEI Baolin;WEI Xueming;HOU Lingli;XU Weilin(Guangxi Key Lab.of Wireless Wideband Commun.and Signal Processing,Guilin Univ.of Elec,Guilin,Guangxi 541004,P.R.China;Chengdu Sino Microelec.Technol.,Co.,Ltd.,Chengdu 610041,P.R.China)

机构地区：[1]桂林电子科技大学广西无线宽带通信与信号处理重点实验室,广西桂林541004 [2]成都华微电子科技有限公司,成都610041

出　　处：《微电子学》2022年第4期656-662,共7页Microelectronics

基　　金：国家自然科学基金地区基金资助项目(62164003,61861009);广西无线宽带通信与信号处理重点实验室主任基金资助项目(GXKL06190110,GXKL06200131,GXKL06200105)。

摘　　要：针对SONTE OC-192、PCIE3.0、USB3.2等协议在串行时钟数据恢复时对抖动容限、环路稳定时间的要求,提出了一种环路带宽自适应调整、半速率相位插值的时钟数据恢复电路(CDR)。设计了自适应控制电路,能适时动态调整环路带宽,实现串行信号时钟恢复过程中环路的快速稳定,提高了时钟数据恢复电路抖动容限。增加了补偿型相位插值控制器,进一步降低了数据接收误码率。该CDR电路基于55 nm CMOS工艺设计,数据输入范围为8~11.5 Gbit/s。采用随机码PRBS31对CDR电路的仿真测试结果表明,稳定时间小于400 ns,输入抖动容限大于0.55UI@10 MHz,功耗小于23 mW。Aiming at the requirements of SONTE OC-192,PCIE3.0,USB3.2 and other protocols for jitter tolerance and loop stability time during serial clock data recovery,a half rate phase interpolation CDR circuit with adaptive loop bandwidth adjustment was proposed.The adaptive control circuit was designed to dynamically adjust the loop bandwidth in a timely manner to achieve fast loop stability during serial signal clock recovery and improve the jitter tolerance of the clock data recovery circuit.A compensated phase interpolation controller was added to further reduce the data reception BER.The CDR circuit was designed in a 55 nm CMOS process with a data input range of 8~11.5 Gbit/s.The random code PRBS31 was used.The simulation test results showed that the stabilization time was less than 400 ns,the input jitter tolerance was more than 0.55UI@10 MHz,and the power consumption was less than 23 mW.

关 键 词：时钟数据恢复 自适应 相位插值 

分 类 号：TN702[电子电信—电路与系统]