基于格的后量子密码算法采样模块的研究及FPGA实现  

Research and FPGA Implementation of Sampling Module for Lattice-based Post-Quantum Cryptography

作　　者：范建南 高献伟[1] 章索 FAN Jiannan;GAO Xianwei;ZHANG Suo(Beijing Electronic Science and Technology Institute,Beijing 100070,P.R.China)

机构地区：[1]北京电子科技学院,北京市100070

出　　处：《北京电子科技学院学报》2022年第3期55-63,共9页Journal of Beijing Electronic Science And Technology Institute

基　　金：北京电子科技学院2021年一流学科建设项目“后量子密码算法核心部件的FPGA高效实现技术研究”(项目编号:20210036Z0401)。

摘　　要：作为算法的核心部件,采样模块的硬件高效实现,能对基于格的后量子密码算法实现起到加速作用。本文深入研究了三种采样算法的设计原理,针对Saber算法的二项分布采样、CRYSTALS-Kyber算法的拒绝-均匀分布采样和NTRU算法的非负相关-三值采样,提出高效的硬件结构设计思路,对采样算法的核心运算单元进行优化改进。最后在FPGA上进行综合实现,并给出不同采样算法的性能分析。与现有文献相比,本文对采样算法的优化设计提高了采样速度,减少了硬件逻辑资源的消耗。As the core component of the algorithm,an efficient hardware implementation of the sampling module could accelerate the implementation of the lattice-based post-quantum cryptography algorithm.In this paper,design principles of three sampling algorithms are studied intensively.For the binomial distribution sampling of the Saber algorithm,the rejection-uniform distribution sampling of the CRYSTALS-Kyber algorithm and the non-negative ternary sampling of the NTRU algorithm,an efficient hardware structure design method is proposed to improve the core operation unit of the sampling algorithms.Finally,the proposed method is implemented on FPGA,and a performance analysis of the sampling algorithms is presented.Compared with the methods in existing literatures,the improved design of the sampling algorithm proposed in this paper improves the sampling speed and reduces the consumption of hardware logic resources.

关 键 词：采样算法 基于格的后量子密码 FPGA 

分 类 号：TN918[电子电信—通信与信息系统]