基于FPGA的SM2加解密算法的优化设计  

Hardware Implementation of SM2 Based on FPGA

作　　者：付元元 高献伟[1] 董秀则[1] FU Yuanyuan;GAO Xianwei;DONG Xiuze(Beijing Electronic Science and Technology Institute,Beijing 100070,P.R.China)

机构地区：[1]北京电子科技学院,北京市100070

出　　处：《北京电子科技学院学报》2022年第3期71-80,共10页Journal of Beijing Electronic Science And Technology Institute

摘　　要：本文提出一种面向现场可编辑门阵列(Field Programmable Gate Array, FPGA)的层次状态机(Hierarchical Finite State Machine, HFSM)实现方案,在频率变化不大的情况下实现面积的优化,以适应逻辑资源较少的国产FPGA。首先介绍了SM2加密算法的基础理论,其次利用FPGA的并行计算的特点,采用模块化编程设计思想,以多层次状态机的方式实现SM2加解密算法。最后在Xilinx Virtex7系列的芯片中运行,结果表明,算法所使用的硬件资源为36486LUTs,相较于一段式有限状态机(Finite State Machine, FSM)实现减少18.3%的资源。In this paper, an HFSM(Hierarchical Finite State Machine) implementation scheme for FPGA(Field Programmable Gate Array) is proposed, which optimizes the area in the case of minor frequency variation to adapt to the domestic FPGA with modest logic resources. First, fundamental principle of the SM2 encryption algorithm is introduced. Then, SM2 encryption and decryption algorithms are implemented in the way of multi-level state machine by using the characteristic of parallel computing of the FPGA and the idea of modular programming design. Finally, the proposed HFSM implementation scheme is experimentally run in a Xilinx virtex7 series chip. Experiment results indicate that the hardware resource for the proposed scheme is 36486 LUTs, which is 18.3% lower than using the FSM(Finite State Machine) implementation scheme.

关 键 词：FPGA SM2 有限状态机 层次状态机 

分 类 号：TN918[电子电信—通信与信息系统]