一种数字电路单粒子翻转试验系统设计  

Design of a Single Event Upset Testing System for Digital Circuits

作　　者：邢泽全 XING Zequan(The 47th Institute of China Electronics Technology Group Corporation,Shenyang 110000,China)

机构地区：[1]中国电子科技集团公司第四十七研究所,沈阳110000

出　　处：《微处理机》2022年第5期6-9,共4页Microprocessors

摘　　要：随着航空航天事业高速发展,抗辐射元器件的使用需求日益旺盛,作为抗辐射性能评估方法之一的单粒子翻转试验愈发体现出重要性。针对单粒子翻转试验条件的设定与优化,设计一种单粒子翻转试验系统。系统可适应绝大部分数字电路的试验需求,采用ARM与FPGA相结合的方式,使用独立设计的DB50分线装置,具备多路输入、多路输出、多路比较的功能。该试验系统驱动能力强、稳定性高,可更有效地进行各类数字电路单粒子翻转效应测试,有助于提高研究效率并缩短开发周期。With the rapid development of aerospace industry, the demand for anti-radiation components is increasing. As one of the evaluation methods of anti-radiation performance, single event upset testing becomes more and more important. Aiming at the setting and optimization of single event upset testing conditions, a single event upset testing system is designed. The system can meet the test requirements of most digital circuits. It adopts the combination of ARM and FPGA, uses the DB50 branching device designed independently, and has the functions of multi-channel input, multi-channel output and multichannel comparison. The testing system has strong driving ability and high stability, and can test the single event upset effect of various digital circuits more effectively, which is helpful to improve the research efficiency and shorten the development cycle.

关 键 词：单粒子翻转 抗辐射性能评价 数字电路测试 

分 类 号：TN406[电子电信—微电子学与固体电子学]