采用反馈时钟检测的锁相环校准电路设计  

Design of Calibration Circuit Using Feedback Clock Detection for Phase Locked Loop

作　　者：张礼怿 张沁枫 俞阳 卓琳[1] ZHANG Liyi;ZHANG Qinfeng;YU Yang;ZHUO Lin(China Electronics Technology Group Corporation No.58 Research Institute,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子与封装》2022年第10期48-55,共8页Electronics & Packaging

摘　　要：采用反馈时钟进行频率检测,设计了一种应用于高频、低抖动频率综合器中的锁相环校准电路。相较于采用参考时钟计数的传统频率校准方法,该方法提高了频率校准精度。配合幅度校准电路交替进行压控振荡器幅度校准和频率校准,可以选取最优幅度和频率控制字,有效提高系统输出时钟抖动性能。高精度频率检测电路和幅度检测电路的电源电压为3.3 V,压控振荡器调谐频率范围为2.7~3.1 GHz,压控增益范围为10~15 MHz/V,初始频率和幅度控制字及最大输出幅度限制可配置。A phase locked loop calibration circuit for a high-frequency low-jitter frequency synthesizer is designed using a feedback clock for frequency detection.The frequency calibration accuracy is improved compared with traditional frequency calibration methods using reference clock counts.With the amplitude calibration circuit to alternately perform the amplitude calibration and frequency calibration of the voltage controlled oscillator,the optimal amplitude and frequency control words will be selected,and the system output clock jitter performance will be effectively improved.The power supply of high-resolution frequency and amplitude detect circuits is 3.3 V,the tuning frequency range of the voltage controlled oscillator is 2.7-3.1 GHz,and the voltage controlled gain range is 10-15 MHz/V.The initial frequency control word,amplitude control word and the maximum output amplitude limit value are configurable.

关 键 词：锁相环 幅度校准 频率校准 压控振荡器 

分 类 号：TN402[电子电信—微电子学与固体电子学]