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作 者:宫凯勋 梁庭[1] 雷程[1] 董志超 赵珠杰 白晨 GONG Kaixun;LIANG Ting;LEI Cheng;DONG Zhichao;ZHAO Zhujie;BAI Chen(Key Laboratory of Instrumentation Science and Dynamic Measurement,Ministry of Education,Taiyuan 030051,China;College of Mechatronics Engineering,North University of China,Taiyuan 030051,China)
机构地区:[1]中北大学仪器科学与动态测试教育部重点实验室,山西太原030051 [2]中北大学机电工程学院,山西太原030051
出 处:《传感器与微系统》2022年第11期27-30,34,共5页Transducer and Microsystem Technologies
基 金:山西省自然科学基金资助项目(201801D221203);山西省重点研发计划项目(201903D121123);中央引导地方科技发展资金资助项目(YDZX20201400001664);高等学校科技创新项目(1810600108MZ)。
摘 要:在碳化硅(SiC)压阻式压力传感器使用溅射剥离再电镀金属作为掩模进行背腔深刻蚀的工艺中,由于电镀过程中背腔侧壁金属的横向生长,实际背腔刻蚀面积小于设计刻蚀面积。针对该问题,基于电化学仿真计算理论,构建了晶圆背腔刻蚀掩模电镀模型,模拟了该工艺下镀层的生长,为芯片设计提供指导。结果表明,晶圆镀层生长厚度从边缘向中心呈对数减小,背腔侧壁位置横向最大沉积速度要大于纵向最大沉积速度,提高镀液电导率可使二者速度比值趋近于1,可以获得整体厚度更加均匀的镀层,实验与仿真镀层厚度偏差在3.41%,背腔侧壁横向生长厚度与纵向生长厚度之比偏差为4.6%,验证了仿真模型的可靠性。In process of SiC piezoresistive pressure sensor using sputtering, stripping and electroplating metal as a mask for back cavity deep etching process, due to the lateral growth of the back cavity sidewall metal during the electroplating process, the actual back cavity etching area is smaller than the designed etching process area.Aiming at this problem, based on the theory of electrochemical simulation calculations, a model for the etching mask plating on the back cavity of the wafer is constructed to simulate the growth of the plating layer under this process and provide guidance for chip design.The results show that the growth thickness of the wafer coating layer decreases logarithmically from the edge to the center, the lateral maximum deposition rate at the sidewall of the back cavity is greater than the vertical maximum deposition rate, increasing the conductivity of the plating solution can make the ratio of the two speeds approach 1. A coating with a more uniform overall thickness can be obtained, the thickness deviation of the experimental and simulated coatings is 3.41 %,and the deviation of the ratio of the lateral growth thickness to the longitudinal growth thickness of the back cavity sidewall is 4.6 %,which verifies the reliability of the simulation model.
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