FPGA千兆以太网接口的IP核设计  

Design of Gigabit Ethernet Interface IP Core Based on FPGA

作　　者：任勇峰[1] 尚辰阳 Ren Yongfeng;Shang Chenyang(Key Laboratory of Instrumentation Science and Dynamic Measurement,Ministry of Education,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《单片机与嵌入式系统应用》2022年第11期49-53,共5页Microcontrollers & Embedded Systems

摘　　要：为了提高飞行物器指令信息和状态信息传输的实时性和可靠性,采用以太网来传输数据。而大多数以太网采用的是未集成协议栈和接口转换模块的物理芯片,从而导致数据无法直接进行传输。针对这一问题,将协议栈和接口转接模块利用IP核封装完成模块化设计、直接进行数据传输。以FPGA作为核心控制器件,将以太网的MAC层接口与UDP/IP的协议栈封装成为可配置的IP核,具有比较强的移植性。网络调试助手和Wireshark软件测试结果显示,IP核性能稳定,且本设备可以实现速率为865.19 Mb/s的数据和指令传输,同时可以完成数据实时发送和接收且不丢包,符合要求。In order to improve the real-time and reliability of missile command information and status information transmission,Ethernet is used to transmit the data.Most Ethernet uses physical chips that do not integrate protocol stack and interface conversion module,so data cannot be transmitted directly.To solve this problem,this paper completes the modular design of protocol stack and interface switching module by using IP core encapsulation for direct data transmission.Taking FPGA as the core control device,the MAC layer interface of Ethernet and the protocol stack of UDP/IP are encapsulated into a configurable IP core,which has strong portability.After being tested by the network debugging assistant and Wireshark software,the results show that the performance of the IP core is stable,and the device can realize the transmission of data and instructions with a speed of 865.19 Mb/s.At the same time,it can send and receive data in real time without packet loss,which meets the requirements.

关 键 词：以太网 FPGA UDP/IP协议 MAC层 IP核 

分 类 号：TN911[电子电信—通信与信息系统]