An FPGA-based LDPC decoder with optimized scale factor of NMS decoding algorithm  

NMS译码算法中优化比例因子的FPGA LDPC译码器

作　　者：LI Jinming ZHAGN Pingping WANG Lanzhu WANG Guodong 李锦明;张萍萍;王兰珠;王国栋(中北大学仪器与电子学院,山西太原030051)

机构地区：[1]School of Instruments and Electronics,North University of China,Taiyuan 030051,China

出　　处：《Journal of Measurement Science and Instrumentation》2022年第4期398-406,共9页测试科学与仪器（英文版）

摘　　要：Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.

关 键 词：LDPC code NMS decoding algorithm variable scale factor QUANTIZATION 

分 类 号：TN911.22[电子电信—通信与信息系统] TN791[电子电信—信息与通信工程]