一种SHA2硬件加速器的设计方法  

Design Methodology of SHA2 Hardware Accelerator

作　　者：马占刚[1] 李婷婷[2] 曹喜信[1] MA Zhangang;LI Tingting;CAO Xixin(Department of Integrated Circuits and Intelligent Systems,School of Software and Microelectronics,Peking University,Beijing 100871;Zhengzhou Technical College,Zhengzhou 450000)

机构地区：[1]集成电路和智能系统系,北京大学软件与微电子学院,北京100871 [2]郑州职业技术学院,郑州450000

出　　处：《北京大学学报（自然科学版）》2022年第6期1007-1014,共8页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：华为“类脑视觉处理技术项目”(YBN2018085207)资助。

摘　　要：针对SHA2硬件吞吐率难以提升的问题,提出一种提升SHA2硬件加速器性能的新方案。1)使用4 Kb的乒乓缓存存储填充好的消息块,使消息填充单元和哈希迭代运算单位两部分硬件电路得以两级流水并行处理。2)在哈希迭代运算中,提取对两轮哈希迭代运算没有依赖性的计算作为预处理,使之与迭代运算的后处理部分形成真正的流水线处理,可以避免以往研究中的伪流水线问题。3)预处理和后处理部分均采用无进位链的3:2压缩器/4:2压缩器和快速加法器等电路,使关键路径明显变短,关键路径延迟明显变小。该方案还支持SHA2双哈希计算:直接对源操作数的摘要进行第二次哈希计算,得到双哈希计算的最后结果,减少外部存储器的访问次数和数据处理,从而提升SHA2双哈希计算的处理速度。In view of difficulty of SHA2 hardware acceleration,a novel performance-improving scheme of SHA2 hardware accelerator is put forth with the following techniques adopted.1)Using 4K bits Ping-Pong buffer storing padded message block,the Message Padding Unit and Hash Calculation Unit can work in parallel as two stages of two-stage pipeline.2)In Hash Calculation Unit,computations which have no dependency on iterative computation are extracted from two folded rounds of hash transformation as pre-computation unit and can work concurrently with post-computation unit in the form of two-stage pipeline rather than pseudo-pipeline which was proposed in the previous researches.3)3:2/4:2 compressors without carry chain and fast adders are adopted in pre-computation unit and post-computation unit to shorten critical path greatly.The proposed scheme also supports double hash computation which directs digest result of source data to the entry of hash iteration unit to obtain final result of double hash of SHA2,improving the performance of SHA2 hardware accelerator.

关 键 词：SHA2 硬件加速器 流水线结构 3:2/4:2压缩器 双哈希计算 

分 类 号：TP311.13[自动化与计算机技术—计算机软件与理论]