基于FPGA的TDC测量中占用资源的研究  

Research on Some Problems of TDC Design Based on FPGA

作　　者：张雄林 王文俊 柏森洋 ZHANG Xiong-Lin;WANG Wen-Jun;BAI Sen-Yang(Automation Research Institute Co.,Ltd.of China South Industries Group Corporation,Mianyang Sichuan621000,China)

机构地区：[1]中国兵器装备集团自动化研究所有限公司,四川绵阳621000

出　　处：《机电产品开发与创新》2022年第6期107-109,共3页Development & Innovation of Machinery & Electrical Products

摘　　要：在对时间间隔进行高精度测量的方法中,设计基于现场变成逻辑门阵列(FPGA)的时间数字转换器是最常见的。本文讨论基于FPGA的TDC设计,设计方法采用将系统分为“粗”测量模块和“细”测量模块的方式。“粗”测量模块的原理是运用直接计数法,“细”测量模块巧妙运用了FPGA内部的快速加法进位链并结合内插法实现。设计基于实际项目需要主要解决TDC在FPGA中占用资源量过大,导致资源分配困难的问题,通过改进进位链的信号传输方式结合程序设计实现。Among the methods of high precision measurement of time interval,the design of time digital converter based on field conversion logic gate array(FPGA)is the most common.This paper discusses the DESIGN of TDC based on FPGA.The design method is to divide the system into"coarse"measurement module and"fine"measurement module.The principle of the"coarse"measurement module is to use the direct counting method,and the"fine"measurement module skillfully uses the fast additive carry chain inside FPGA and the interpolation method.Based on the actual project needs,the design mainly solves the problem that TDC occupies too much resources in FPGA,which leads to the difficulty of resource allocation.It is realized by improving the signal transmission mode of carry chain and combining with program design.

关 键 词：时间数字转换器 现场可编程逻辑门阵列 进位链 

分 类 号：TM935[电气工程—电力电子与电力传动]