一种低功耗倍频延迟锁相环设计  

Design of a Low-power multiplying DLL

作　　者：诸荣臻 潘意杰 唐中[1] ZHU Rongzhen;PAN Yijie;TANG Zhong(Zhejiang University,Hangzhou 311200,Zhejiang,China;Ningbo Institute of Information Technology Application,CAS,Ningbo 315040,Zhejiang,China;Department of Computer Science and Technology,Tsinghua University,Beijing 100084,China)

机构地区：[1]浙江大学,浙江杭州311200 [2]中国科学院信息技术应用研究院,浙江宁波315040 [3]清华大学计算机科学与技术系,北京100084

出　　处：《微电子学与计算机》2022年第12期93-99,共7页Microelectronics & Computer

基　　金：宁波市“2025科技创新”重大专项(2019B10082)。

摘　　要：多相时钟是集成电路的关键模块之一,在模拟数字转换器(Analog-to-Digital Converter,ADC),或是时间数字转换器(Time-to-Digital Converter,TDC)等电路中有大量的应用.多相时钟通常由延迟锁相环(Delay-Locked Loop,DLL)与锁相环(Phase-Locked Loop,PLL)产生.然而传统DLL无法倍频,PLL会有抖动累积等问题.此外,DLL与PLL的功耗通常较大.针对这些问题,本文提出了一种低功耗防错锁倍频延迟锁相环(Multiplying Delay-Locked Loop,MDLL).该设计采用一种低功耗的电荷泵结构,以及能切换为压控振荡器的压控延迟线,使电路功能在DLL与PLL之间切换,在倍频的同时能够周期地消除抖动累积.同时加入了防错锁电路,以避免MDLL锁定在错误的频率.基于HHGrace 0.11μm COMS工艺进行了流片验证,芯片面积约为0.03 mm 2.测试结果表明,此电路能够将输入参考时钟倍频32倍输出,输出时钟频率范围为54.4 MHz-92.8 MHz,电路功耗为216μW–312μW.在输出时钟频率为80 MHz的情况下,均方根抖动为116.3ps(0.93%).Multiphase clock is one of the key modules of integrated circuit.It is widely used in analog-to-digital converter(ADC),time-to-digital converter(TDC)and other circuits.Multiphase clocks are usually generated by delay-locked loops(DLL)or phase-locked loops(PLL).However,DLLs cannot multiply frequency,PLLs suffer from jitter accumulation problems.In addition,DLLs and PLLs usually have high power consumption.To solve these problems,a low power multiplying delay-locked loop(MDLL)is proposed,which uses a low power charge pump structure and a voltage controlled delay line that can be switched to a voltage controlled oscillator to switch the circuit function between DLL and PLL.The MDLL can eliminate jitter accumulation while multiplying frequency.By adding a circuit for preventing false lock,the MDLL work at the right frequency.The circuit is implemented in HHGrace 0.11μm COMS process,and occupies only 0.03mm2.The test results show that the circuit can multiply the input reference clock frequency by 32 x,the output clock frequency range is 54.4MHz to 92.8MHz,and the circuit power consumption is 216μW-312μW.When the output clock frequency is 80MHz,the measured RMS jitter is 116.3ps(0.93%).

关 键 词：延迟锁相环 时钟抖动 低功耗 电荷泵 

分 类 号：TN911.8[电子电信—通信与信息系统]