基于随机森林的网表级时序预测模型  

Random forest-based netlist-level timing prediction

作　　者：蒋政涛 贺旭 李琼 傅智勇 JIANG Zhengtao;HE Xu;LI Qiong;FU Zhiyong(College of Computer Science and Electronic Engineering,Hunan University,Changsha 410082,Hunan,China)

机构地区：[1]湖南大学信息科学与工程学院计算机工程系,湖南长沙410082

出　　处：《微电子学与计算机》2022年第12期107-114,共8页Microelectronics & Computer

基　　金：国家自然科学基金项目(61872136,U19A2062)。

摘　　要：在超大规模集成电路设计中,时序分析的准确性对指导时序优化,保证芯片时序收敛和运行性能至关重要.目前,时序分析绝大多数都是采用商用签核(Sign-off)工具时序报告,作为主要依据.在逻辑综合阶段,由于缺少物理布局布线之后的模块位置和布线结果等信息,因此很难得到准确的电容电阻等寄生参数,用于预测其对应的Sign-off时序.为提高逻辑综合阶段时序预测的准确性,在给定工艺库的情况下,以电路网表作为输入,采用线负载模型对网表的电容电阻等进行估算,并在此基础上利用Elmore Delay模型计算时延作为时序特征.在时序模型训练阶段,提取训练集电路网表的时序特征,以训练模型对应的Sign-off时序结果为标准,采用机器学习中的随机森林算法进行模型训练,包括构建三个模型:互连线时延(Wire delay)、互连线信号转换时延(Wire slew),以及输出负载(Output load).在测试阶段,本文以同工艺库下,新的电路网表作为测试集,输入给训练后的时序模型进行预测.我们的方法与商用工具PrimeTime相比,在Wire delay和Wire slew的Sign-off结果预测上,平均一致性(Correlation)分别提高了49%、37%.此外,我们的方法所预测的Output load与Sign-off结果的一致性在0.99以上.In VLSI design,the accuracy of timing analysis is very important to guide design optimization for timing closure and performance improvement.In the logic synthesis stage,it is difficult to predict the timing due to the lack of placement,and routing information.To improve the accuracy of timing prediction at the logic netlist-level,wireload model is applied to predict the RC parameters,and the Elmore delay model is also used for timing feature calculation.In model training phase,the timing features of the training set are extracted.Taking the corresponding sign-off timing report as the ground-truth,the random forest algorithm is applied for model training.In our method,three models are constructed,including:wire delay model,wire slew model,and output load model.In inference phase,the testing set under the same process library as the training set is used for prediction evaluation.Compared with the commercial tool PrimeTime,the correlation between the sign-off result and our predicted wire delay and wire slew is increased by 49%and 37%,respectively.In addition,the correlation of our output load is more than 0.99.

关 键 词：静态时序分析 随机森林 逻辑综合 网表级 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]