高速串行接口全链路有效抖动模型与测试相干分析  

Analysis of the Full-Link Valid Jitter Model and Test of High-Speed Serial Interfaces

作　　者：龙志军 张作群 陆小凡 丁学伟 欧阳可青 LONG Zhi-jun;ZHANG Zuo-qun;LU Xiao-fan;DING Xue-wei;OUYANG Ke-qing(Sanechips Technology Co.,Ltd)

机构地区：[1]深圳市中兴微电子技术有限公司

出　　处：《中国集成电路》2022年第12期43-50,共8页China lntegrated Circuit

摘　　要：接口带宽是5G、AI、云计算等信息系统核心芯片的关键属性。简单扩展传输通道数目可成倍增加传输带宽,但封装与连接器引脚增加会导致结构难题,密集的互连线会恶化串扰,高速串行接口技术必不可少。在过去的10多年中,高速串行接口在传输速度和体系架构上有飞跃式的进步,从10G发展至112G/224G,这要求对传输过程中各种非理想因素的建模和分析更加精细,业界为此建立了一套全新的方法学。抖动是高速串行接口设计和应用中最大的挑战之一,本文从全链路视角介绍超高速串行接口的有效抖动模型,并给出测试方法,为高速系统设计提供参考与指导。Interface bandwidth is a key attribute of core chips in information systems such as 5G,AI,and cloud com-puting.The high-speed serial interface technology is indispensable.In the past decade or so,high-speed serial inter-faces have made rapid progress in transmission speed and system architecture,and have evolved from 10 G to 112 G/224 G.This requires finer modeling and analysis of various non-ideal factors in the transmission process.To this end,a new set of methodology has been established in the industry.Jitter is one of the biggest challenges in high-speed serial interface design and application.This document describes the effective jitter model of ul-tra-high-speed serial interfaces from the perspective of full links,and provides test methods to provide reference and guidance for high-speed system design.

关 键 词：高速串行接口 有效抖动 信号完整性 电源完整性 全链路 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构] TN40[自动化与计算机技术—计算机科学与技术]