基于FPGA的SOC原型验证时钟方案研究  

Research on Clock Scheme of SOC Prototype Verification based on FPGA

作　　者：李文晶 LI Wen-jing(Shanghai Fudan Microelectronics Group Company Limited)

机构地区：[1]上海复旦微电子集团股份有限公司

出　　处：《中国集成电路》2022年第12期51-55,共5页China lntegrated Circuit

摘　　要：在基于FPGA的SOC原型验证过程中,由于SOC芯片的时钟网络比较庞大并且复杂,不能直接用在FPGA芯片上,所以需要对原型验证时钟方案进行研究。本文针对SOC芯片原型验证的时钟方案,从时钟网络简化、多片FPGA时钟同步、门控时钟转换和时钟降频四个方面来分析,给出一套完整的时钟解决方案及设计方法。In the process of SOC prototype verification based on FPGA,the clock network of SOC chip is relatively large and complex,which can not be directly used in FPGA chip,so the clock scheme of prototype verification needs to be studied.In this paper,the clock scheme of SOC chip prototype verification is analyzed from four aspects:clock network simplification,multi-chip FPGA clock synchronization,gated clock conversion and clock frequency reduc-tion,and a complete clock solution and design method are presented.

关 键 词：SOC原型验证 FPGA 时钟网络 时钟同步 门控时钟 时钟降频 

分 类 号：TN791[电子电信—电路与系统] TN47