13位高无杂散动态范围的SAR ADC  

13-bit High Spurious-Free Dynamic Range SAR ADC

作　　者：杨志新 Maureen Willis 高博[1] 龚敏[1] YANG Zhixin;WILLIS Maureen;GAO Bo;GONG Min(School of Physics,Sichuan University,Chengdu 610065,China)

机构地区：[1]四川大学物理学院,成都610065

出　　处：《电子与封装》2022年第12期46-52,共7页Electronics & Packaging

摘　　要：基于标准0.18μm CMOS工艺,设计了一款采样率为500 kSa/s的13位逐次逼近型模数转换器(SAR ADC)芯片。该转换器内集成了多路复用器、比较器、SAR逻辑电路和数模转换器(DAC)电容阵列等模块,实现了数字位的串行输出。使用7+6分段式电容阵列及下极板采样和电荷重分配原理,有效降低了ADC整体电容值及功耗。使用两级预放大的比较器和电荷存储技术降低了失调误差,比较器精度为0.3 mV。在2.5 V电源电压和500 kSa/s的采样率下,后仿真结果表明,ADC的无杂散动态范围为97.14 dB,信噪比为78.78 dB,有效位数为12.78 bit。Based on the standard 0.18μm CMOS process,a 13-bit successive approximation analog-to-digital converter(SAR ADC)chip with a sampling rate of 500 kSa/s is designed.The converter integrates multiplexer,comparator,SAR logic circuit,digital-to-analog converter(DAC)capacitor array and other modules.It achieves serial digital output.By using 7+6 segmented capacitor array with bottom plate sampling and the principle of charge redistribution,the overall capacitance and power consumption of the ADC are effectively reduced.Two-stage pre-amplified comparator and charge storage technology are used to reduce the offset error.The accuracy of the comparator is 0.3 mV.The post-simulation results under the power supply voltage of 2.5 V and the sampling frequency of 500 kSa/s show that the spurious-free dynamic range of ADC is 97.14 dB,the signal-to-noise ratio is 78.78 dB,and the effective number of bits is 12.78 bit.

关 键 词：逐次逼近型模数转换器 比较器 无杂散动态范围 电荷重分配 

分 类 号：TN402[电子电信—微电子学与固体电子学]