一种晶上系统互连网络的容错感知结构  

Fault-tolerant awareness structure for network on wafer

作　　者：王明楠 刘勤让[1] 刘冬培 汤先拓 Wang Mingnan;Liu Qinrang;Liu Dongpei;Tang Xiantuo(Institute of Information Technology,Information Engineering University,Zhengzhou 450001,China)

机构地区：[1]信息工程大学信息技术研究所,郑州450001

出　　处：《计算机应用研究》2023年第2期533-538,共6页Application Research of Computers

基　　金：国家科技重大专项资助项目(2016ZX01012101);首届国防科技创新大赛资助项目

摘　　要：晶上系统融合预制件组装和晶圆集成等先进理念,是延续摩尔定律的一种新方法。由于晶圆基板本身制造良率和拼接的不确定性,晶上系统存在路由节点故障或链路故障等问题。为提高系统容错性,提出了一种基于2D-Mesh晶上互连网络的容错感知结构。在Mesh环中交叉使用主副感知器用于获取故障信息,再将其广播至全局路由节点实现数据包的避障绕行,缓解数据包在路由过程中可能发生的阻塞。实验仿真表明该结构在多种故障模式下,相较于传统容错路由算法有更高的饱和注入率,能够有效提高系统容错性,降低局部故障导致的性能影响。System on wafer that incorporate advanced concepts such as dielets assembly and wafer integration are a new way to continue Moore′s Law.Due to the uncertainty of the manufacturing yield and the splicing process in the wafer substrate network,the system on wafer has problems such as routing node failure or link failure.In order to improve the fault tolerance of the system,this paper proposed a fault-tolerant perceptron structure based on 2D-Mesh network on wafer.It used the primary and secondary perceptrons interchangeably in the Mesh ring to obtain the fault information of interconnected routing nodes,and used the broadcast mechanism to notify the global routing.The node could avoid obstacles and detours of data packets,and relieved the blocking of data packets that may occur in the routing process.Experimental simulations show that this structure has higher saturation injection rate than traditional fault-tolerant routing algorithms under various failure modes,and can effectively improve the fault tolerance of the system and reduce the performance impact caused by partial failures.

关 键 词：晶上系统 晶上互连网络 容错结构 感知器 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]