基于FPGA的格密码关键运算模块的设计与实现  

Design and Implementation for Crucial Modules of Lattice-based Cryptography Based on FPGA

作　　者：韩炼冰[1] 房利国[1] 王松[1] 刘鸿博[1] 杨敏旭 HAN Lianbing;FANG Liguo;WANG Song;LIU Hongbo;YANG Mingxu(No.30 Institute of CETC,Chengdu Sichuan 610041,China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《通信技术》2022年第12期1613-1617,共5页Communications Technology

摘　　要：格密码是后量子密码中的一项重要技术,为提高格密码运算效率,提出了一种格密码中多项式乘法的硬件实现方法。该方法利用现场可编程门阵列(Field Program Gate Array,FPGA)内部存储器存放多项式系数,采用乒乓结构提高存储器并行读写速度,并通过预计算和预缩放简化计算过程,降低计算复杂度。同时,采用多级流水线技术,减少存取时间和蝶形运算等待时间,提升整体编译频率,提高运算性能。评估结果表明,该方法最大工作频率达到了320 MHz,完成一次1 024项多项式乘法运算的时间为41μs。Lattice-based cryptography is an important technique in post-quantum cryptography. In order to improve the computational efficiency of lattice-based cryptography, a hardware implementation of polynomial multiplication in lattice-based cryptography is proposed in this paper. The method uses FPGA(Field Program Gate Array) internal memory to store polynomial coefficients, adopts a ping-pong structure to improve memory parallel read and write speed, and simplifies the computation process by pre-computing and pre-scaling to reduce computational complexity. At the same time, it uses multi-level pipeline to reduce access time and butterfly operation time, enhance the overall compilation frequency, and improve computing performance. The evaluation results indicate that the maximum frequency of the method reaches 320 MHz,and the calculation time of 1 024 polynomial coefficients multiplication is 41 μs.

关 键 词：后量子密码 现场可编程门阵列 数论变换 多项式乘法 蝶形运算 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]