基于UVM的AXI4总线自验证平台设计  

Design of Self-Verification Platform for AXI4 Bus Based on UVM

作　　者：隋金雪[1] 张霞[2] 郁添林 SUI Jin-xue;Melissa ZHANG;YU Tian-lin(School of Electronics and Information Engineering,Shandong Technology and Business University,Yantai Shandong 264026,China;Advanced Institute of Information Technology Peking University,Hangzhou Zhejiang 311215,China)

机构地区：[1]山东工商学院电子与信息工程学院,山东烟台264003 [2]北京大学信息技术高等研究院,浙江杭州311215

出　　处：《计算机仿真》2023年第1期345-348,488,共5页Computer Simulation

基　　金：山东省自然科学基金(2016ZRB019JQ);浙江省重点研发计划项目(2020C01SA100208)。

摘　　要：基于通用验证方法学(Universal Verification Methodology, UVM)搭建了可用于AXI4总线协议的验证平台,该验证环境针对基于AMBA总线的AXI4 IP功能的验证需求搭建。该验证平台结合通用功能组件设计总线功能模型,设置受约束的随机激励与定向测试,构造不同的测试用例,完成验证结果的自动校验,提高了验证效率和平台的可移植性。在AXI4多主多从的互联结构下,对乱序传输、突发传输以及混合交叉读写类型等进行充分验证。验证进度可从仿真日志、覆盖率指标以及波形图直观判断,搭建的验证平台完成了AXI4总线的验证任务。Based on Universal Verification Methodology(UVM),a verification platform that can be used for the AXI4 bus protocol was built. Based on the AMBA bus, the verification environment was built to fulfill the verification requirements of the AXI4 IP function. The verification platform combined general functional components to design the bus function model, set up constrained random excitation and directional tests, construct different test cases, complete automatic comparison of verification results, and improve the portability of the platform. Under the AXI4 multi-master and multi-slave interconnection structure, out-of-order transmission, burst transmission, and mixed interleaved read-write types were fully verified. The verification results can be directly checked from the simulation log, function coverage and waveform. The built verification platform has completed the verification task of the AXI4 bus.

关 键 词：通用验证方法学 总线功能模型 验证平台 自动校验 仿真日志 

分 类 号：TP47[自动化与计算机技术]