检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:李震[1] 王丹 高达[1] 邢伟荣[1] LI Zhen;WANG Dan;GAO Da;XING Wei-rong(North China Research Institute of Electro-Optics,Beijing 10015,China)
出 处:《红外》2023年第2期18-23,共6页Infrared
基 金:国家重点研发计划资助课题(2018YFB2200301);研究生科研与实践创新计划校级项目(2021XKT1254)。
摘 要:硅与碲镉汞之间的外延碲化镉缓冲层能够减小外延过程中产生的高达107cm^(-2)的位错密度,高温热退火是抑制材料位错的有效方法之一。传统的离位退火技术会导致工艺不稳定和杂质污染等,而原位退火则可有效解决这些问题。利用原位退火技术对分子束外延生长的硅基碲化镉材料进行了位错抑制研究。对厚度约为9μm的碲化镉材料进行了6个周期不同温度的热循环退火,并阐释了不同退火温度对硅基碲化镉材料位错的抑制效果。采用统计位错腐蚀坑密度的方法对比了退火前后材料的位错变化。可以发现,在退火温度为520℃时,位错密度可以达到1.2×10^(6)cm^(-2),比未进行退火的CdTe材料的位错密度降低了半个数量级。The epitaxial CdTe buffer layer between silicon and HgCdTe can reduce dislocation density of up to 10~7 cm^(-2)generated during epitaxial process.High-temperature thermal annealing is one of the effective methods to suppress dislocations in materials.The traditional out of place annealing technology will lead to process instability and impurity pollution,and in-situ annealing can effectively solve these problems.Dislocation suppress of Si-based CdTe grown by molecular beam epitaxy(MBE)was studied using in-situ annealing technique.The CdTe material with a thickness of about 9μm was subjected to six cycles of thermal cycling annealing at different temperatures.The effect of different annealing temperatures on the dislocation suppression of Si-based CdTe material was explained.Statistical dislocation etch-pits density method was used to compare the dislocation changes of materials before and after annealing.It can be found that the dislocation density can reach 1.2×10^(6)cm^(-2)when the annealing temperature is 520℃,which is 0.5 orders of magnitude lower than that of the CdTe material without annealing.
分 类 号:TN214[电子电信—物理电子学]
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.15