低功耗时钟树  

Low power clock tree

作　　者：朱佳琪 陈岚[1,3] 王海永 ZHU Jiaqi;CHEN Lan;WANG Haiyong(Institute of Microelectronics of China Academy of Science,Beijing 100029,China;University of Chinese Academy of Science,Beijing 100049,China;Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology,Beijing 100029,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049 [3]三维及纳米集成电路设计自动化技术北京市重点实验室,北京100029

出　　处：《中国科学院大学学报（中英文）》2023年第2期203-207,共5页Journal of University of Chinese Academy of Sciences

基　　金：北京市科技计划-国产EDA工具产业链应用推广示范平台项目(Z201100004220005)资助。

摘　　要：提出一种最大可能满足时序且功耗最小化的时钟树设计方法,该方法以扇出数和驱动器选择策略作为低功耗时钟树设计的优化变量。针对不同的扇出数,以选择标准单元库中全部反相器/缓冲器的驱动器选择策略为参考策略,与本文提出的3种选取部分反相器/缓冲器的驱动器选择策略进行对比分析,同时提出以时钟树的时钟偏差值和功耗值组成的优值因子作为评价各种驱动器选择策略的标准。实验结果表明,以优值因子为评价标准,时钟树设计中的最优扇出数与驱动器选择策略相关性不大,且本文提出的3种驱动器选择策略都比参考策略要好,其中在优值因子最好的一个策略中,典型情况下时钟树功耗降低5.82%。最后,总结出一种基于优值因子的低功耗时钟树设计方法。This paper proposes a clock tree design method that meets timing as much as possible and minimizes power consumption. This method uses fanout number and driver selection strategy as the optimization variables for low-power clock tree design. For different fanout numbers, we take the driver selection strategy of selecting all inverters/buffers in the standard cell library as the reference strategy, and comparing and analyzing the three driver selection strategies with partial inverters/buffers proposed in this article. At the same time, the merit factor composed of the clock skew and power consumption of the clock tree is proposed as the criterion for evaluating various driver selection strategies. The experimental results show that with the merit factor as the evaluation criterion, the optimal fanout number in the clock tree design has little correlation with the driver selection strategy, and the three driver selection strategies proposed in this paper are better than the reference strategy. In the strategy with the best merit factor, the power consumption of the clock tree is reduced by 5.82% typically. Finally, this paper presents a low power clock tree design method based on merit factor.

关 键 词：低功耗 扇出 驱动器 时钟树 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN432