基于多项式基的Camellia算法S盒硬件优化  

Hardware Optimization of S-box of Camellia Algorithm Based on Polynomial Basis

作　　者：李艳俊 张伟国[2] 葛耀东 王克 LI Yanjun;ZHANG Weiguo;GE Yaodong;WANG Ke(Information Industry Information Security Evaluation Center,the 15th Research Institute of China Electronics Technology Group Corporation,Beijing 100083,China;Beijing Institute of Electronic Science and Technology,Beijing 100070,China)

机构地区：[1]中国电子科技集团公司第十五研究所信息产业信息安全测评中心,北京100083 [2]北京电子科技学院,北京100070

出　　处：《电子与信息学报》2023年第3期921-928,共8页Journal of Electronics & Information Technology

基　　金：广西密码学与信息安全重点实验室开放课题(GCIS201912);北京高校“高精尖”学科建设项目(20210101Z0401)。

摘　　要：该文提出一种基于不可约多项式的Camellia算法S盒的代数表达式,并给出了该表达式8种不同的同构形式。然后,结合Camellia算法S盒的特点,基于理论证明给出一种基于多项式基的S盒优化方案,此方法省去了表达式中的部分线性操作。相对于同一种限定门的方案,在中芯国际(SMIC)130 nm工艺库中,该文方案减少了9.12%的电路面积;在SMIC 65 nm工艺库中,该文方案减少了8.31%的电路面积。最后,根据Camellia算法S盒设计中的计算冗余,给出了2类完全等价的有限域的表述形式,此等价形式将对Camellia算法S盒的优化产生积极影响。An algebraic expression for the S-box of Camellia’s algorithm based on irreducible polynomials is proposed in this paper,and eight different isomorphic expressions are also given.Then combined with the characteristics of S-box,an optimization scheme based on polynomial basis is given by theoretical proof,in which some redundant linear operations are reduced.Compared with the same gate-limited scheme the circuit area is saved by 9.12%in the Semiconductor Manufacturing International Corporation(SMIC)130 nm process library and by 8.31%in the SMIC 65 nm process library.Finally,according to the computational redundancy in the design of the S-box of Camellia algorithm,two completely equivalent representations on the finite field are given,which will have a positive impact on the optimization of the S-box of Camellia algorithm.

关 键 词：有限域 多项式基 正规基 Camellia算法 S盒 

分 类 号：TN918.4[电子电信—通信与信息系统]