面向RISC-V嵌入式处理器的浮点单元设计与移植  

Design and porting of FPU for RISC-V embedded processor

作　　者：唐俊龙[1,2] 吴圳羲 卢英龙 黄智昌 邹望辉 TANG Junlong;WU Zhenxi;LU Yinglong;HUANG Zhichang;ZOU Wanghui(School of Physics&Electronic Science,Changsha University of Technology&Sicence,Changsha 410114,China;Key Laboratory of Flexible Electronic Material Genetic Engineering of Hunan Province,Changsha 410114,China)

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410114 [2]柔性电子材料基因工程湖南省重点实验室,湖南长沙410114

出　　处：《电子设计工程》2023年第7期119-123,131,共6页Electronic Design Engineering

基　　金：柔性电子材料基因工程湖南省重点实验室开放基金(202015);长沙理工大学研究生科研创新项目(6110201-000101201)。

摘　　要：针对软件实现浮点运算的速度无法满足RISC-V嵌入式处理器浮点运算的需求,设计了一种由浮点加法器和浮点乘法器构成的浮点单元(FPU),其中浮点乘法器提出了新型的Wallace树压缩结构,提高了压缩速率。在“蜂鸟E203”处理器中,完成浮点指令的译码模块与派遣模块的设计,实现FPU模块的移植。基于Simc180 nm工艺,使用Sysnopsys公司的Design Compile、VCS工具对FPU进行功能验证和综合,仿真结果表明,浮点加法器的关键路径延时为10.17 ns,相比于串行浮点加法器延时缩短23%,浮点乘法器的压缩结构关键路径延时为0.27 ns,相比传统Wallace树压缩延时缩短10%,移植前后的FPU运算结果一致。The speed of floating⁃point caculation realized by software can not meet the needs of RISC⁃V embedded processor,a Floating⁃Point Unit(FPU)composed of floating⁃point adder and floating⁃point multiplier was designed,the floating⁃point multiplier proposes a innovative Wallace tree compression structure and improved compression rate.For the"Hummingbird E203"processor,the design of decoding module and dispatch module of the floating⁃point instruction was completed,and the FPU module is ported to the processor.Based on the Simc180 nm process,FPU was functionally verified and synthesized by the Design Compile and VCS tools.The simulation results show that the critical path delay of the floating⁃point adder is 10.17 ns,it compared with serial floating⁃point adder,the delay is reduced by 23%,the critical path delay of the compression structure of the floating⁃point multiplier is 0.27 ns,which is 10%shorter than the compression delay of the traditional Wallace tree,and that the calculation results of FPU before and after porting are the same.

关 键 词：RISC-V处理器 two-path WALLACE树 浮点单元 移植 

分 类 号：TN492[电子电信—微电子学与固体电子学]