一种面向多核系统的PLB转AXI桥接器设计  

Design of PLB to AXI bus bridge for multi-core system

作　　者：贾一鸣 李磊[1] 肖建青[1] JIA Yiming;LI Lei;XIAO Jianqing(Xi'an Microelectronics Technology Institute,Xi'an 710054,Shaanxi,China)

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2023年第4期117-124,共8页Microelectronics & Computer

基　　金：航天科技集团青年拔尖项目(TT2022-015)。

摘　　要：针对多核系统中PLB和AXI总线间协议转换的需求,首先研究了总线协议与PowerPC处理器的访存行为,进一步研究了流水控制、读写叠加等高效率转换策略,最后研究了面向多核系统应用的缓存一致性维护策略.针对命令信号、读数据信号和写数据信号独立传输的特点,设计多通道流水线结构,既实现了命令与数据的流水并行也实现了读事务与写事务的叠加并行;在多通道流水线结构的基础上,提出一种流水并行+可变长描述符的2级加速转换技术,通过给予流水线输入更连续的总线事务,实现更高的总线转换效率;借鉴Cache表项的结构和维护策略,提出基于动态命中预测的缓存一致性维护技术,加速一致性读命令的进程.最终,实现一种高性能的PLB到AXI总线桥设计,达到总线协议行为全覆盖、命令转换低延迟的目标.总线桥应用于某款基于双核PowerPC处理器的异构多核体系结构芯片,解决了SoC系统内PLB到AXI总线的高效、高可靠转换问题,并在65 nm工艺下完成流片.For the need of convention between PLB and AXI protocol in multi-core system,the bus protocol and memory access behavior of PowerPC processor are studied firstly.The high-efficiency conversion strategies such as pipeline control and read-write superposition are further studied.Finally,the cache coherency maintenance strategy for multi-core system applications is studied.According to the independent characteristics of command signals,read data signals and write data signals,a multi-channel pipeline structure is designed.It realizes the pipelining parallelism of commands and data,and also the interleaving parallelism of read transactions and write transactions.On the basis of pipeline structure,a 2-stage accelerated conversion technology with pipeline-parallel and variable length descriptor is proposed.By importing more continuous bus transactions into the pipeline structure,higher bus conversion efficiency is realized.Refer to the structure and maintenance strategy of cache entries,a cache coherence technology based on dynamic hit prediction is proposed to speed up the process of read commands.Finally,a PLB to AXI bus bridge with full protocol coverage and low conversion delay is realized.The bus bridge is applied to a heterogeneous multi-core architecture chip based on dual-core PowerPC processor,which solves the problem of efficient and reliable conversion from PLB to AXI bus in SoC system.The above design was successfully produced in 65 nm process.

关 键 词：桥接器 流水线 描述符 命中预测 缓存一致性 

分 类 号：TN47[电子电信—微电子学与固体电子学]