一种应用于嵌入式FPGA卷积神经网络加速器的串行乘法器设计  

A Serial Multiplier Design for Embedded FPGA Convolutional Neural Networks Accelerator

作　　者：杨军 李倍 陈新伟[2] 张凯 梁科[1] 李国峰[1] Yang Jun;Li Bei;Chen Xinwei;Zhang Kai;Liang Ke;Li Guofeng(Tianjin Key Laboratory of Optoelectronic Sensor and Sensing Network Technology,College of Electronic Information and Optical Engineering,Nankai University,Tianjin 300350,China;Fujian Provincial Key Laboratory of Information Processing and Intelligent Control(Minjiang University),Fuzhou 350121,China;AutoBrain(Tianjin)Technology Co Ltd,Tianjin 300300,China)

机构地区：[1]南开大学电子信息与光学工程学院,天津市光电传感器与传感网络技术重点实验室,天津300350 [2]福建省信息处理与智能控制重点实验室(闽江学院),福建福州350121 [3]奥特贝睿(天津)科技有限公司,天津300300

出　　处：《南开大学学报（自然科学版）》2023年第1期8-12,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：电子信息与控制福建省高校工程研究中心开放课题(EIC1702)。

摘　　要：为满足神经网络中多种位宽数据计算的动态需求,从而提升硬件资源的能效,提出一种位串行乘法器设计—以1 bit的计算逻辑为核心,将多位数据的并行乘操作转化为每个周期进行1位数据乘操作的串行计算方式.为进一步提升硬件资源的利用率,在此基础上提出多通道位串行乘法器阵列同时进行多个数据的并行计算.实验结果显示,在最大支持位宽为8 bit的条件下,单通道位串行乘法器的LUT资源使用量是并行乘法器的41%,LUT资源有效利用率是并行乘法器的1.32倍;当通道数为8时,多通道位串行乘法器阵列的LUT资源使用量是多通道并行乘法器阵列的29%.该结构实现了硬件资源和性能之间的平衡——提高硬件资源的利用率从而提升计算效能.In order to meet the dynamic requirements of multiple width data computation in neural network and improve the energy efficiency of hardware resources, a design of bit serial multiplier is proposed,which takes 1-bit computing logic as the core and converts the parallel multiplication operation of multi-bit data into a serial computation mode of 1-bit data multiplication operation every cycle. In order to further improve the utilization of hardware resources, a multi-channel bit serial multiplier array is proposed for parallel computation of multiple data. The experimental results show that under the condition that the maximum supported bit width is 8 bits, the LUT resource usage of single-channel bit serial multiplier is 41%of that of parallel multiplier, and the effective utilization of LUT resource is 1.32x of that of parallel multiplier. When the number of channels is 8, the LUT resource usage of the multi-channel bit serial multiplier array is 29% of that of the multi-channel parallel multiplier array. This architecture achieves a balance between hardware resources and performance-increasing the utilization of hardware resources to improve computing performance.

关 键 词：卷积神经网络 FPGA 位串行乘法器 多通道乘法器阵列 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]