一种集成于OrCAD Capture CIS的SIP原理图规则检查错误反标工具  

A SIP schematic rule checking error back-marking tool integrated in OrCAD Capture CIS

作　　者：郑利华 锡瑞杰 李鑫鹏 付方发[2] 王启昂 王进祥[2] ZHENG LiHua;XI Ruijie;LI Xinpeng;FU Fangfa;WANG Qiang;WANG Jinxiang(The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi 214072,China;Harbin Institute of Technology,Harbin 150001,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214072 [2]哈尔滨工业大学,黑龙江哈尔滨150001

出　　处：《微电子学与计算机》2023年第3期132-138,共7页Microelectronics & Computer

基　　金：国家自然基金资助项目(U2032209)。

摘　　要：系统级封装(System in Packet,SiP)技术将多个子系统集成在一个封装内,具有组装方式灵活、研发周期短等优势,在电子设备小型化的进程中具有广阔的发展前景.在SiP的设计流程中,原理图设计是否正确往往决定了整体设计的成败.然而,原理图设计中出现的连接性错误通常需要工程人员花费大量时间进行查找对比,从而确定错误的位置.为了提高原理图连接性错误检查的效率,提出了一种应用于SiP系统级封装原理图设计阶段的连接性规则检查错误反标工具,由工具命令语言(Tool Command Language,TCL)开发.该工具以插件形式集成于OrCAD Capture CIS X具中,可以配合已有的原理图规则检查工具,使用户可以通过图形界面获取并分析规则检查工具生成的有效错误信息,并将错误信息清晰直观的反标于原理图的相应位置.通过对由26页原理图组成的测试系统进行错误反标测试,该工具可以在数秒内将原理图中的连接性错误信息反标在原理图的对应位置,使设计人员可以快速定位错误的位置,有效的提高了原理图设计阶段连接性检查的效率.System-in-Packet(SiP)technology integrates multiple subsystems in one package,which has the advantages of flexible assembly method and short development cycle,and has broad development prospects in the process of miniaturization of electronic equipment.In the SiP design process,whether the schematic design is correct often determines the success or failure of the overall design.However,connectivity errors in schematic designs often require engineers to spend a lot of time looking for comparisons to pinpoint the location of the error.In order to improve the efficiency of schematic connectivity error checking,this paper proposes a connectivity rule checking error back-marking tool applied to the SiP system-in-package schematic design stage.The tool is integrated into the OrCAD Capture CIS tool in the form of a plug-in,which can cooperate with the existing schematic rule checking tool,so that users can obtain and analyze the valid error information generated by the rule checking tool through the graphical interface,and the error information is clear and intuitive.By perfonning an error back-labeling test on a test system consisting of 26 pages of schematics,the tool can back-label the connectivity error infoimation in the schematic to the corresponding location on the schematic within seconds,allowing designers to quickly locate the wrong location,which effectively improves the efficiency of the connectivity check in the schematic design stage.

关 键 词：SIP EDA工具 错误检查 

分 类 号：TN402[电子电信—微电子学与固体电子学]