紧耦合异构线程处理器  

Tightly coupled heterogeneous thread processor

作　　者：李文青 齐寒 肖子原 朱威浦 王剑[1,2] LI Wenqing;QI Han;XIAO Ziyuan;ZHU Weipu;WANG Jian(State Key Laboratory of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049)

机构地区：[1]处理器芯片全国重点实验室(中国科学院计算技术研究所),北京100190 [2]中国科学院大学计算机科学与技术学院,北京100049

出　　处：《高技术通讯》2023年第2期113-123,共11页Chinese High Technology Letters

基　　金：中国科学院战略性先导科技专项(XDC05020100)资助项目。

摘　　要：异构计算为系统达到更高的性能功耗比提供了新的思路和方向,但异构系统中中央处理器(CPU)和加速器协同执行任务的过程中大量的控制信号传输和数据搬运始终是系统性能的一个重要瓶颈。对此,本文提出了一种紧耦合异构线程处理器结构,包括一个硬件CPU线程和一个硬件加速器线程,二者采用流水线紧耦合的硬件线程间通信接口和共享存储的方式降低了通信代价,大幅提高了系统性能。为验证该结构的优势,本文在开源BOOM核的基础上设计了硬件线程间通信接口,实现了一个具有高级加密标淮(AES)加速器的紧耦合异构线程处理器,并在现场可编程门阵列(FPGA)上进行了评估。结果显示,在加密任务中,该处理器吞吐量约是Intel Comet Lake使用AES指令集(AES-NI)的5.7倍,是BOOM平台上仅使用通用指令的4000倍。实验进一步验证了通过CPU和加速器快速通信实现的细粒度并行可以取得更多的性能收益。由此得出结论:该结构能敏捷地将加速器整合到CPU周围,有效降低了通信时间,实现CPU线程和加速器线程的细粒度并行,有效地发挥出异构计算的优势,取得可观的性能收益。Heterogeneous computing provides a new idea and direction for the system to achieve a higher performancepower ratio.However,a large amount of control signal and data interaction is always an important bottleneck for the system performance in the process of central processing unit(CPU)and accelerator cooperatively executing tasks in heterogeneous systems.To address this problem,a tightly coupled heterogeneous thread processor architecture is proposed,which includes a hardware CPU thread and a hardware accelerator thread.Both of them use pipeline tightly coupled hardware thread communication interface and shared memory to reduce the communication cost and greatly improve the system performance.To verify the advantages of this architecture,a hardware inter-thread communication interface is designed based on the open source BOOM core,a tightly coupled heterogeneous thread processor is implemented with an advanced encryption standard(AES)encryption and decryption accelerator,and evaluation is performed on field programmable gate array(FPGA).The results show that in encryption tasks,the processor throughput is about 4.7 times higher than that of Intel Comet Lake using AES new instructions(AES-NI)in encryption tasks and 4000 times higher than that of the BOOM platform using only general-purpose instructions.The experiment further verifies that more performance gains can be achieved with fine-grained parallelism obtained by fast communication between the CPU and accelerator.This leads to the conclusion that the architecture can agilely integrate the accelerator around the CPU,effectively reduce the communication time and achieve fine-grained parallelism of CPU threads and accelerator threads,effectively exploit the advantages of heterogeneous computing,and obtain considerable performance gains.

关 键 词：异构计算 异构接口 紧耦合 通信 细粒度并行 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]