CMOS phase-locked loops in ISSCC 2023  

作　　者：Zhao Zhang 

机构地区：[1]State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China [2]Center of Materials Science and Optoelectronics Engineering,University of Chinese Academy of Sciences,Beijing 100049,China

出　　处：《Journal of Semiconductors》2023年第5期17-18,共2页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Grant Nos.62222409 and62174153);Beijing Municipal Science and Technology Project(Grant No.Z211100007921019)。

摘　　要：High-performance phase-locked loops(PLL)are widely used in modern system-on chips(So C)including the ultrahigh-speed wireless/wireline communication(e.g.5G/6G transceivers,over-100-Gbps Ser Des transceivers),high resolution mm-wave radars,ultra-low power internet-of-thing(Io T),and high-sampling-rate data converters.In the 2023 IEEE International Solid-State Circuits Conference(ISSCC 2023).

关 键 词：ISSCC TRANSCEIVER WIRELESS 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN911.8